From e2409c333508f3de648727440907ee1b9b6a876d Mon Sep 17 00:00:00 2001
From: Patrick Plenefisch <simonpatp@gmail.com>
Date: Sun, 23 Jul 2023 17:38:34 -0400
Subject: [PATCH] ice40: Implement simple SB_HFOSC and SB_LFOSC for simulation

This doesn't use all the features, notably trim, nor does it
simulate the first 100us, instead working on the first cycle
---
 techlibs/ice40/cells_sim.v | 48 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 8943815bf..bade31094 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2678,6 +2678,37 @@ module SB_HFOSC(
 );
 parameter TRIM_EN = "0b0";
 parameter CLKHF_DIV = "0b00";
+
+`ifndef BLACKBOX
+	// 96mhz hidden clock
+	reg hidden_clock = 0;
+
+	// all 4 options for the clock divider
+	reg [3:0] divisions = 0;
+
+	always begin
+		while (CLKHFPU) begin
+			#5208 hidden_clock = 0;
+			#5208 hidden_clock = 1;
+		end
+		// when PowerUp is deasserted, wait to resynchronize the clock on it's edge
+		@(posedge CLKHFPU);
+	end
+
+	// TODO: simulate the 100us of "not yet ready"/power stability early on
+
+	always @(posedge hidden_clock) begin
+		divisions <= divisions + 1;
+	end
+
+	localparam index = CLKHF_DIV == "0b00" ? 0 : 
+				   CLKHF_DIV == "0b01" ? 1 : 
+				   CLKHF_DIV == "0b10" ? 2 : 
+				   CLKHF_DIV == "0b11" ? 3 : 0;
+
+	assign CLKHF = CLKHFEN && CLKHFPU && divisions[index];
+
+`endif
 endmodule
 
 (* blackbox *)
@@ -2686,6 +2717,23 @@ module SB_LFOSC(
 	input CLKLFEN,
 	output CLKLF
 );
+
+`ifndef BLACKBOX
+	reg clock = 0;
+	always begin
+		while (CLKLFPU) begin
+			#100000000 clock = 0;
+			#100000000 clock = 1;
+		end
+		// when PowerUp is deasserted, wait to resynchronize the clock on its edge
+		@(posedge CLKLFPU);
+	end
+
+	// TODO: simulate the 100us of "not yet ready"/power stability early on
+
+	assign CLKLF = CLKLFEN && CLKLFPU && clock;
+
+`endif
 endmodule
 
 (* blackbox *)