From 2468b391bfb146005569941835079e496fd32c3b Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 24 Jan 2026 01:48:15 +0000 Subject: [PATCH] Make `compare_signals` produce a total order. Currently when `s1` and `s2` are different bits of the same wire, it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to return false. This means the calling code will call `assign_map.add()` for both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2` should be consistently preferred. So fix that by preferring the `SigBit` with the smaller bit offset. --- passes/opt/opt_clean.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3892c7581..661871d87 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -271,6 +271,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo return conns.check_any(s2); } + if (w1 == w2) + return s2.offset < s1.offset; + if (w1->port_output != w2->port_output) return w2->port_output;