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	Merge pull request #3629 from YosysHQ/micko/clang_fixes
Fixes for some of clang scan-build detected issues
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						commit
						245884a101
					
				
					 15 changed files with 39 additions and 23 deletions
				
			
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			@ -393,6 +393,7 @@ struct BugpointPass : public Pass {
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				}
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			}
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		}
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		delete design_copy;
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		return nullptr;
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	}
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			@ -118,6 +118,9 @@ struct DesignPass : public Pass {
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		std::string save_name, load_name, as_name, delete_name;
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		std::vector<RTLIL::Module*> copy_src_modules;
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		if (!design)
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			log_cmd_error("No default design.\n");
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		size_t argidx;
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		for (argidx = 1; argidx < args.size(); argidx++)
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		{
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			@ -280,7 +283,7 @@ struct DesignPass : public Pass {
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				done[mod->name] = prefix;
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			}
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			while (!queue.empty())
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			while (!queue.empty() && copy_from_design)
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			{
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				pool<Module*> old_queue;
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				old_queue.swap(queue);
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			@ -64,6 +64,7 @@ struct OptFfInvWorker
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			log_assert(d_inv == nullptr);
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			d_inv = port.cell;
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		}
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		if (!d_inv) return false;
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		if (index.query_is_output(ff.sig_q))
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			return false;
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			@ -140,6 +141,7 @@ struct OptFfInvWorker
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			log_assert(d_lut == nullptr);
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			d_lut = port.cell;
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		}
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		if (!d_lut) return false;
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		if (index.query_is_output(ff.sig_q))
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			return false;
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			@ -167,6 +169,7 @@ struct OptFfInvWorker
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			log_assert(q_inv == nullptr);
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			q_inv = port.cell;
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		}
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		if (!q_inv) return false;
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		ff.flip_rst_bits({0});
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		ff.sig_q = q_inv->getPort(ID::Y);
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			@ -302,7 +302,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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		ce.assign_map.apply(rstval);
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		ce.assign_map.apply(sig);
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		if (rstval == sig) {
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		if (rstval == sig && sync_level) {
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			if (sync_level->type == RTLIL::SyncType::ST1)
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				insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal);
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			else
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