Merge remote-tracking branch 'origin/master' into xc7srl

passes/opt/opt_expr.cc

@@ -155,6 +155,13 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 			new_b.append_bit(it.first.second);
 		}
 
+		if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
+			log("  Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
+			module->connect(new_y, new_b);
+			module->connect(new_conn);
+			continue;
+		}
+
 		RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
 
 		c->setPort("\\A", new_a);

passes/sat/Makefile.inc

@@ -9,4 +9,6 @@ OBJS += passes/sat/assertpmux.o
 OBJS += passes/sat/clk2fflogic.o
 OBJS += passes/sat/async2sync.o
 OBJS += passes/sat/supercover.o
+OBJS += passes/sat/fmcombine.o
+OBJS += passes/sat/mutate.o
 

passes/sat/fmcombine.cc

@@ -0,0 +1,341 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "kernel/celltypes.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct opts_t
+{
+	bool fwd = false;
+	bool bwd = false;
+	bool nop = false;
+};
+
+struct FmcombineWorker
+{
+	const opts_t &opts;
+	Design *design;
+	Module *original = nullptr;
+	Module *module = nullptr;
+	IdString orig_type, combined_type;
+
+	FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
+			opts(opts), design(design), original(design->module(orig_type)),
+			orig_type(orig_type), combined_type("$fmcombine" + orig_type.str())
+	{
+	}
+
+	SigSpec import_sig(SigSpec sig, const string &suffix)
+	{
+		SigSpec newsig;
+		for (auto chunk : sig.chunks()) {
+			if (chunk.wire != nullptr)
+				chunk.wire = module->wire(chunk.wire->name.str() + suffix);
+			newsig.append(chunk);
+		}
+		return newsig;
+	}
+
+	void import_prim_cell(Cell *cell, const string &suffix)
+	{
+		Cell *c = module->addCell(cell->name.str() + suffix, cell->type);
+		c->parameters = cell->parameters;
+		c->attributes = cell->attributes;
+
+		for (auto &conn : cell->connections())
+			c->setPort(conn.first, import_sig(conn.second, suffix));
+	}
+
+	void import_hier_cell(Cell *cell)
+	{
+		if (!cell->parameters.empty())
+			log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", log_id(original), log_id(cell));
+
+		FmcombineWorker sub_worker(design, cell->type, opts);
+		sub_worker.generate();
+
+		Cell *c = module->addCell(cell->name.str() + "_combined", sub_worker.combined_type);
+		// c->parameters = cell->parameters;
+		c->attributes = cell->attributes;
+
+		for (auto &conn : cell->connections()) {
+			c->setPort(conn.first.str() + "_gold", import_sig(conn.second, "_gold"));
+			c->setPort(conn.first.str() + "_gate", import_sig(conn.second, "_gate"));
+		}
+	}
+
+	void generate()
+	{
+		if (design->module(combined_type)) {
+			// log("Combined module %s already exists.\n", log_id(combined_type));
+			return;
+		}
+
+		log("Generating combined module %s from module %s.\n", log_id(combined_type), log_id(orig_type));
+		module = design->addModule(combined_type);
+
+		for (auto wire : original->wires()) {
+			module->addWire(wire->name.str() + "_gold", wire);
+			module->addWire(wire->name.str() + "_gate", wire);
+		}
+		module->fixup_ports();
+
+		for (auto cell : original->cells()) {
+			if (design->module(cell->type) == nullptr) {
+				import_prim_cell(cell, "_gold");
+				import_prim_cell(cell, "_gate");
+			} else {
+				import_hier_cell(cell);
+			}
+		}
+
+		for (auto &conn : original->connections()) {
+			module->connect(import_sig(conn.first, "_gold"), import_sig(conn.second, "_gold"));
+			module->connect(import_sig(conn.first, "_gate"), import_sig(conn.second, "_gate"));
+		}
+
+		if (opts.nop)
+			return;
+
+		CellTypes ct;
+		ct.setup_internals_eval();
+		ct.setup_stdcells_eval();
+
+		SigMap sigmap(module);
+
+		dict<SigBit, SigBit> data_bit_to_eq_net;
+		dict<Cell*, SigSpec> cell_to_eq_nets;
+		dict<SigSpec, SigSpec> reduce_db;
+		dict<SigSpec, SigSpec> invert_db;
+
+		for (auto cell : original->cells())
+		{
+			if (!ct.cell_known(cell->type))
+				continue;
+
+			for (auto &conn : cell->connections())
+			{
+				if (!cell->output(conn.first))
+					continue;
+
+				SigSpec A = import_sig(conn.second, "_gold");
+				SigSpec B = import_sig(conn.second, "_gate");
+				SigBit EQ = module->Eq(NEW_ID, A, B);
+
+				for (auto bit : sigmap({A, B}))
+					data_bit_to_eq_net[bit] = EQ;
+
+				cell_to_eq_nets[cell].append(EQ);
+			}
+		}
+
+		for (auto cell : original->cells())
+		{
+			if (!ct.cell_known(cell->type))
+				continue;
+
+			bool skip_cell = !cell_to_eq_nets.count(cell);
+			pool<SigBit> src_eq_bits;
+
+			for (auto &conn : cell->connections())
+			{
+				if (skip_cell)
+					break;
+
+				if (cell->output(conn.first))
+					continue;
+
+				SigSpec A = import_sig(conn.second, "_gold");
+				SigSpec B = import_sig(conn.second, "_gate");
+
+				for (auto bit : sigmap({A, B})) {
+					if (data_bit_to_eq_net.count(bit))
+						src_eq_bits.insert(data_bit_to_eq_net.at(bit));
+					else
+						skip_cell = true;
+				}
+			}
+
+			if (!skip_cell) {
+				SigSpec antecedent = SigSpec(src_eq_bits);
+				antecedent.sort_and_unify();
+
+				if (GetSize(antecedent) > 1) {
+					if (reduce_db.count(antecedent) == 0)
+						reduce_db[antecedent] = module->ReduceAnd(NEW_ID, antecedent);
+					antecedent = reduce_db.at(antecedent);
+				}
+
+				SigSpec consequent = cell_to_eq_nets.at(cell);
+				consequent.sort_and_unify();
+
+				if (GetSize(consequent) > 1) {
+					if (reduce_db.count(consequent) == 0)
+						reduce_db[consequent] = module->ReduceAnd(NEW_ID, consequent);
+					consequent = reduce_db.at(consequent);
+				}
+
+				if (opts.fwd)
+					module->addAssume(NEW_ID, consequent, antecedent);
+
+				if (opts.bwd)
+				{
+					if (invert_db.count(antecedent) == 0)
+						invert_db[antecedent] = module->Not(NEW_ID, antecedent);
+
+					if (invert_db.count(consequent) == 0)
+						invert_db[consequent] = module->Not(NEW_ID, consequent);
+
+					module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
+				}
+			}
+		}
+	}
+};
+
+struct FmcombinePass : public Pass {
+	FmcombinePass() : Pass("fmcombine", "combine two instances of a cell into one") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    fmcombine [options] module_name gold_cell gate_cell\n");
+		// log("    fmcombine [options] @gold_cell @gate_cell\n");
+		log("\n");
+		log("This pass takes two cells, which are instances of the same module, and replaces\n");
+		log("them with one instance of a special 'combined' module, that effectively\n");
+		log("contains two copies of the original module, plus some formal properties.\n");
+		log("\n");
+		log("This is useful for formal test benches that check what differences in behavior\n");
+		log("a slight difference in input causes in a module.\n");
+		log("\n");
+		log("    -fwd\n");
+		log("        Insert forward hint assumptions into the combined module.\n");
+		log("\n");
+		log("    -bwd\n");
+		log("        Insert backward hint assumptions into the combined module.\n");
+		log("        (Backward hints are logically equivalend to fordward hits, but\n");
+		log("        some solvers are faster with bwd hints, or even both -bwd and -fwd.)\n");
+		log("\n");
+		log("    -nop\n");
+		log("        Don't insert hint assumptions into the combined module.\n");
+		log("        (This should not provide any speedup over the original design, but\n");
+		log("        strangely sometimes it does.)\n");
+		log("\n");
+		log("If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		opts_t opts;
+		Module *module = nullptr;
+		Cell *gold_cell = nullptr;
+		Cell *gate_cell = nullptr;
+
+		log_header(design, "Executing FMCOMBINE pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-o" && argidx+1 < args.size()) {
+			// 	filename = args[++argidx];
+			// 	continue;
+			// }
+			if (args[argidx] == "-fwd") {
+				opts.fwd = true;
+				continue;
+			}
+			if (args[argidx] == "-bwd") {
+				opts.bwd = true;
+				continue;
+			}
+			if (args[argidx] == "-nop") {
+				opts.nop = true;
+				continue;
+			}
+			break;
+		}
+		if (argidx+2 == args.size())
+		{
+			string gold_name = args[argidx++];
+			string gate_name = args[argidx++];
+			log_cmd_error("fmcombine @gold_cell @gate_cell call style is not implemented yet.");
+		}
+		else if (argidx+3 == args.size())
+		{
+			IdString module_name = RTLIL::escape_id(args[argidx++]);
+			IdString gold_name = RTLIL::escape_id(args[argidx++]);
+			IdString gate_name = RTLIL::escape_id(args[argidx++]);
+
+			module = design->module(module_name);
+			if (module == nullptr)
+				log_cmd_error("Module %s not found.\n", log_id(module_name));
+
+			gold_cell = module->cell(gold_name);
+			if (gold_cell == nullptr)
+				log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gold_name), log_id(module));
+
+			gate_cell = module->cell(gate_name);
+			if (gate_cell == nullptr)
+				log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gate_name), log_id(module));
+		}
+		else
+		{
+			log_cmd_error("Invalid number of arguments.\n");
+		}
+		// extra_args(args, argidx, design);
+
+		if (opts.nop && (opts.fwd || opts.bwd))
+			log_cmd_error("Option -nop can not be combined with -fwd and/or -bwd.\n");
+
+		if (!opts.nop && !opts.fwd && !opts.bwd)
+			opts.fwd = true;
+
+		if (gold_cell->type != gate_cell->type)
+			log_cmd_error("Types of gold and gate cells do not match.\n");
+		if (!gold_cell->parameters.empty())
+			log_cmd_error("Gold cell has unresolved instance parameters.\n");
+		if (!gate_cell->parameters.empty())
+			log_cmd_error("Gold cell has unresolved instance parameters.\n");
+
+		FmcombineWorker worker(design, gold_cell->type, opts);
+		worker.generate();
+		IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", log_id(gold_cell), log_id(gate_cell)));
+
+		Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
+		cell->attributes = gold_cell->attributes;
+		cell->add_strpool_attribute("\\src", gate_cell->get_strpool_attribute("\\src"));
+
+		log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell));
+
+		for (auto &conn : gold_cell->connections())
+			cell->setPort(conn.first.str() + "_gold", conn.second);
+		module->remove(gold_cell);
+
+		for (auto &conn : gate_cell->connections())
+			cell->setPort(conn.first.str() + "_gate", conn.second);
+		module->remove(gate_cell);
+	}
+} FmcombinePass;
+
+PRIVATE_NAMESPACE_END

passes/sat/mutate.cc

@@ -0,0 +1,905 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct mutate_t {
+	string mode;
+	pool<string> src;
+	IdString module, cell;
+	IdString port, wire;
+	int portbit = -1;
+	int ctrlbit = -1;
+	int wirebit = -1;
+	bool used = false;
+};
+
+struct mutate_opts_t {
+	int seed = 0;
+	std::string mode;
+	pool<string> src;
+	IdString module, cell, port, wire;
+	int portbit = -1;
+	int ctrlbit = -1;
+	int wirebit = -1;
+
+	IdString ctrl_name;
+	int ctrl_width = -1, ctrl_value = -1;
+
+	int pick_cover_prcnt = 80;
+
+	int weight_cover = 500;
+
+	int weight_pq_w = 100;
+	int weight_pq_b = 100;
+	int weight_pq_c = 100;
+	int weight_pq_s = 100;
+
+	int weight_pq_mw = 100;
+	int weight_pq_mb = 100;
+	int weight_pq_mc = 100;
+	int weight_pq_ms = 100;
+};
+
+void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, const mutate_t &entry)
+{
+	if (!opts.mode.empty() && opts.mode != entry.mode)
+		return;
+
+	if (!opts.src.empty()) {
+		bool found_match = false;
+		for (auto &s : opts.src) {
+			if (entry.src.count(s))
+				found_match = true;
+		}
+		if (!found_match)
+			return;
+	}
+
+	if (!opts.module.empty() && opts.module != entry.module)
+		return;
+
+	if (!opts.cell.empty() && opts.cell != entry.cell)
+		return;
+
+	if (!opts.port.empty() && opts.port != entry.port)
+		return;
+
+	if (opts.portbit >= 0 && opts.portbit != entry.portbit)
+		return;
+
+	if (opts.ctrlbit >= 0 && opts.ctrlbit != entry.ctrlbit)
+		return;
+
+	if (!opts.wire.empty() && opts.wire != entry.wire)
+		return;
+
+	if (opts.wirebit >= 0 && opts.wirebit != entry.wirebit)
+		return;
+
+	database.push_back(entry);
+}
+
+struct xs128_t
+{
+	uint32_t x = 123456789;
+	uint32_t y = 0, z = 0, w = 0;
+
+	xs128_t(int seed = 0) : w(seed) {
+		next();
+		next();
+		next();
+	}
+
+	void next() {
+		uint32_t t = x ^ (x << 11);
+		x = y, y = z, z = w;
+		w ^= (w >> 19) ^ t ^ (t >> 8);
+	}
+
+	int operator()() {
+		next();
+		return w & 0x3fffffff;
+	}
+
+	int operator()(int n) {
+		if (n < 2)
+			return 0;
+		while (1) {
+			int k = (*this)(), p = k % n;
+			if ((k - p + n) <= 0x40000000)
+				return p;
+		}
+	}
+};
+
+struct coverdb_t
+{
+	dict<string, int> src_db;
+	dict<tuple<IdString, IdString>, int> wire_db;
+	dict<tuple<IdString, IdString, int>, int> wirebit_db;
+
+	void insert(const mutate_t &m) {
+		if (!m.wire.empty()) {
+			wire_db[tuple<IdString, IdString>(m.module, m.wire)] = 0;
+			wirebit_db[tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit)] = 0;
+		}
+		for (auto &s : m.src) {
+			src_db[s] = 0;
+		}
+	}
+
+	void update(const mutate_t &m) {
+		if (!m.wire.empty()) {
+			wire_db.at(tuple<IdString, IdString>(m.module, m.wire))++;
+			wirebit_db.at(tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit))++;
+		}
+		for (auto &s : m.src) {
+			src_db.at(s)++;
+		}
+	}
+
+	int score(const mutate_t &m) {
+		int this_score = m.src.empty() ? 0 : 1;
+		if (!m.wire.empty()) {
+			this_score += wire_db.at(tuple<IdString, IdString>(m.module, m.wire)) ? 0 : 5;
+			this_score += wirebit_db.at(tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit)) ? 0 : 1;
+		}
+		for (auto &s : m.src) {
+			this_score += src_db.at(s) ? 0 : 5;
+		}
+		return this_score;
+	}
+};
+
+struct mutate_queue_t
+{
+	pool<mutate_t*, hash_ptr_ops> db;
+
+	mutate_t *pick(xs128_t &rng, coverdb_t &coverdb, const mutate_opts_t &opts) {
+		mutate_t *m = nullptr;
+		if (rng(100) < opts.pick_cover_prcnt) {
+			vector<mutate_t*> candidates, rmqueue;
+			int best_score = -1;
+			for (auto p : db) {
+				if (p->used) {
+					rmqueue.push_back(p);
+					continue;
+				}
+				int this_score = coverdb.score(*p);
+				if (this_score > best_score) {
+					best_score = this_score;
+					candidates.clear();
+				}
+				if (best_score == this_score)
+					candidates.push_back(p);
+			}
+			for (auto p : rmqueue)
+				db.erase(p);
+			if (!candidates.empty())
+				m = candidates[rng(GetSize(candidates))];
+		}
+		if (m == nullptr) {
+			while (!db.empty()) {
+				int i = rng(GetSize(db));
+				auto it = db.element(i);
+				mutate_t *p = *it;
+				db.erase(it);
+				if (p->used == false) {
+					m = p;
+					break;
+				}
+			}
+		}
+		return m;
+	}
+
+	void add(mutate_t *m) {
+		db.insert(m);
+	}
+};
+
+template <typename K, typename T>
+struct mutate_chain_queue_t
+{
+	dict<K, T> db;
+
+	mutate_t *pick(xs128_t &rng, coverdb_t &coverdb, const mutate_opts_t &opts) {
+		while (!db.empty()) {
+			int i = rng(GetSize(db));
+			auto it = db.element(i);
+			mutate_t *m = it->second.pick(rng, coverdb, opts);
+			if (m != nullptr)
+				return m;
+			db.erase(it);
+		}
+		return nullptr;
+	}
+
+	template<typename... Args>
+	void add(mutate_t *m, K key, Args... args) {
+		db[key].add(m, args...);
+	}
+};
+
+template <typename K, typename T>
+struct mutate_once_queue_t
+{
+	dict<K, T> db;
+
+	mutate_t *pick(xs128_t &rng, coverdb_t &coverdb, const mutate_opts_t &opts) {
+		while (!db.empty()) {
+			int i = rng(GetSize(db));
+			auto it = db.element(i);
+			mutate_t *m = it->second.pick(rng, coverdb, opts);
+			db.erase(it);
+			if (m != nullptr)
+				return m;
+		}
+		return nullptr;
+	}
+
+	template<typename... Args>
+	void add(mutate_t *m, K key, Args... args) {
+		db[key].add(m, args...);
+	}
+};
+
+void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N, xs128_t &rng)
+{
+	std::vector<mutate_t> new_database;
+	coverdb_t coverdb;
+
+	int total_weight = opts.weight_cover + opts.weight_pq_w + opts.weight_pq_b + opts.weight_pq_c + opts.weight_pq_s;
+	total_weight += opts.weight_pq_mw + opts.weight_pq_mb + opts.weight_pq_mc + opts.weight_pq_ms;
+
+	if (N >= GetSize(database))
+		return;
+
+	mutate_once_queue_t<tuple<IdString, IdString>, mutate_queue_t> primary_queue_wire;
+	mutate_once_queue_t<tuple<IdString, IdString, int>, mutate_queue_t> primary_queue_bit;
+	mutate_once_queue_t<tuple<IdString, IdString>, mutate_queue_t> primary_queue_cell;
+	mutate_once_queue_t<string, mutate_queue_t> primary_queue_src;
+
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<IdString, mutate_queue_t>> primary_queue_module_wire;
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<pair<IdString, int>, mutate_queue_t>> primary_queue_module_bit;
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<IdString, mutate_queue_t>> primary_queue_module_cell;
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<string, mutate_queue_t>> primary_queue_module_src;
+
+	for (auto &m : database)
+	{
+		coverdb.insert(m);
+
+		if (!m.wire.empty()) {
+			primary_queue_wire.add(&m, tuple<IdString, IdString>(m.module, m.wire));
+			primary_queue_bit.add(&m, tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit));
+			primary_queue_module_wire.add(&m, m.module, m.wire);
+			primary_queue_module_bit.add(&m, m.module, pair<IdString, int>(m.wire, m.wirebit));
+		}
+
+		primary_queue_cell.add(&m, tuple<IdString, IdString>(m.module, m.cell));
+		primary_queue_module_cell.add(&m, m.module, m.cell);
+
+		for (auto &s : m.src) {
+			primary_queue_src.add(&m, s);
+			primary_queue_module_src.add(&m, m.module, s);
+		}
+	}
+
+	vector<mutate_t*> cover_candidates;
+	int best_cover_score = -1;
+	bool skip_cover = false;
+
+	while (GetSize(new_database) < N)
+	{
+		int k = rng(total_weight);
+
+		k -= opts.weight_cover;
+		if (k < 0) {
+			while (!skip_cover) {
+				if (cover_candidates.empty()) {
+					best_cover_score = -1;
+					for (auto &m : database) {
+						if (m.used || m.src.empty())
+							continue;
+						int this_score = -1;
+						for (auto &s : m.src) {
+							if (this_score == -1 || this_score > coverdb.src_db.at(s))
+								this_score = coverdb.src_db.at(s);
+						}
+						log_assert(this_score != -1);
+						if (best_cover_score == -1 || this_score < best_cover_score) {
+							cover_candidates.clear();
+							best_cover_score = this_score;
+						}
+						if (best_cover_score == this_score)
+							cover_candidates.push_back(&m);
+					}
+					if (best_cover_score == -1) {
+						skip_cover = true;
+						break;
+					}
+				}
+
+				mutate_t *m = nullptr;
+				while (!cover_candidates.empty())
+				{
+					int idx = rng(GetSize(cover_candidates));
+					mutate_t *p = cover_candidates[idx];
+					cover_candidates[idx] = cover_candidates.back();
+					cover_candidates.pop_back();
+
+					if (p->used)
+						continue;
+
+					int this_score = -1;
+					for (auto &s : p->src) {
+						if (this_score == -1 || this_score > coverdb.src_db.at(s))
+							this_score = coverdb.src_db.at(s);
+					}
+
+					if (this_score != best_cover_score)
+						continue;
+
+					m = p;
+					break;
+				}
+
+				if (m != nullptr) {
+					m->used = true;
+					coverdb.update(*m);
+					new_database.push_back(*m);
+					break;
+				}
+			}
+			continue;
+		}
+
+#define X(__wght, __queue)                               \
+    k -= __wght;                                         \
+    if (k < 0) {                                         \
+      mutate_t *m = __queue.pick(rng, coverdb, opts);    \
+      if (m != nullptr) {                                \
+        m->used = true;                                  \
+        coverdb.update(*m);                              \
+        new_database.push_back(*m);                      \
+      };                                                 \
+      continue;                                          \
+    }
+
+		X(opts.weight_pq_w, primary_queue_wire)
+		X(opts.weight_pq_b, primary_queue_bit)
+		X(opts.weight_pq_c, primary_queue_cell)
+		X(opts.weight_pq_s, primary_queue_src)
+
+		X(opts.weight_pq_mw, primary_queue_module_wire)
+		X(opts.weight_pq_mb, primary_queue_module_bit)
+		X(opts.weight_pq_mc, primary_queue_module_cell)
+		X(opts.weight_pq_ms, primary_queue_module_src)
+#undef X
+	}
+
+	std::swap(new_database, database);
+
+	int covered_src_cnt = 0;
+	int covered_wire_cnt = 0;
+	int covered_wirebit_cnt = 0;
+
+	for (auto &it : coverdb.src_db)
+		if (it.second)
+			covered_src_cnt++;
+
+	for (auto &it : coverdb.wire_db)
+		if (it.second)
+			covered_wire_cnt++;
+
+	for (auto &it : coverdb.wirebit_db)
+		if (it.second)
+			covered_wirebit_cnt++;
+
+	log("Covered %d/%d src attributes (%.2f%%).\n", covered_src_cnt, GetSize(coverdb.src_db), 100.0 * covered_src_cnt / GetSize(coverdb.src_db));
+	log("Covered %d/%d wires (%.2f%%).\n", covered_wire_cnt, GetSize(coverdb.wire_db), 100.0 * covered_wire_cnt / GetSize(coverdb.wire_db));
+	log("Covered %d/%d wire bits (%.2f%%).\n", covered_wirebit_cnt, GetSize(coverdb.wirebit_db), 100.0 * covered_wirebit_cnt / GetSize(coverdb.wirebit_db));
+}
+
+void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N)
+{
+	std::vector<mutate_t> database;
+	xs128_t rng(opts.seed);
+
+	for (auto module : design->selected_modules())
+	{
+		if (!opts.module.empty() && module->name != opts.module)
+			continue;
+
+		SigMap sigmap(module);
+		dict<SigBit, int> bit_user_cnt;
+
+		for (auto wire : module->wires()) {
+			if (wire->name[0] == '\\' && wire->attributes.count("\\src"))
+				sigmap.add(wire);
+		}
+
+		for (auto cell : module->cells()) {
+			for (auto &conn : cell->connections()) {
+				if (cell->output(conn.first))
+					continue;
+				for (auto bit : sigmap(conn.second))
+					bit_user_cnt[bit]++;
+			}
+		}
+
+		for (auto wire : module->selected_wires())
+		{
+			for (SigBit bit : SigSpec(wire))
+			{
+				SigBit sigbit = sigmap(bit);
+
+				if (bit.wire == nullptr || sigbit.wire == nullptr)
+					continue;
+
+				if (!bit.wire->port_id != !sigbit.wire->port_id) {
+					if (bit.wire->port_id)
+						sigmap.add(bit);
+					continue;
+				}
+
+				if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
+					if (bit.wire->name[0] == '\\')
+						sigmap.add(bit);
+					continue;
+				}
+			}
+		}
+
+		for (auto cell : module->selected_cells())
+		{
+			if (!opts.cell.empty() && cell->name != opts.cell)
+				continue;
+
+			for (auto &conn : cell->connections())
+			{
+				for (int i = 0; i < GetSize(conn.second); i++) {
+					mutate_t entry;
+					entry.module = module->name;
+					entry.cell = cell->name;
+					entry.port = conn.first;
+					entry.portbit = i;
+
+					for (auto &s : cell->get_strpool_attribute("\\src"))
+						entry.src.insert(s);
+
+					SigBit bit = sigmap(conn.second[i]);
+					if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
+						for (auto &s : bit.wire->get_strpool_attribute("\\src"))
+							entry.src.insert(s);
+						entry.wire = bit.wire->name;
+						entry.wirebit = bit.offset;
+					}
+
+					entry.mode = "inv";
+					database_add(database, opts, entry);
+
+					entry.mode = "const0";
+					database_add(database, opts, entry);
+
+					entry.mode = "const1";
+					database_add(database, opts, entry);
+
+					entry.mode = "cnot0";
+					entry.ctrlbit = rng(GetSize(conn.second));
+					if (entry.ctrlbit != entry.portbit && conn.second[entry.ctrlbit].wire)
+						database_add(database, opts, entry);
+
+					entry.mode = "cnot1";
+					entry.ctrlbit = rng(GetSize(conn.second));
+					if (entry.ctrlbit != entry.portbit && conn.second[entry.ctrlbit].wire)
+						database_add(database, opts, entry);
+				}
+			}
+		}
+	}
+
+	log("Raw database size: %d\n", GetSize(database));
+	if (N != 0) {
+		database_reduce(database, opts, N, rng);
+		log("Reduced database size: %d\n", GetSize(database));
+	}
+
+	std::ofstream fout;
+
+	if (!filename.empty()) {
+		fout.open(filename, std::ios::out | std::ios::trunc);
+		if (!fout.is_open())
+			log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
+	}
+
+	int ctrl_value = opts.ctrl_value;
+
+	for (auto &entry : database) {
+		string str = "mutate";
+		if (!opts.ctrl_name.empty())
+			str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
+		str += stringf(" -mode %s", entry.mode.c_str());
+		if (!entry.module.empty())
+			str += stringf(" -module %s", log_id(entry.module));
+		if (!entry.cell.empty())
+			str += stringf(" -cell %s", log_id(entry.cell));
+		if (!entry.port.empty())
+			str += stringf(" -port %s", log_id(entry.port));
+		if (entry.portbit >= 0)
+			str += stringf(" -portbit %d", entry.portbit);
+		if (entry.ctrlbit >= 0)
+			str += stringf(" -ctrlbit %d", entry.ctrlbit);
+		if (!entry.wire.empty())
+			str += stringf(" -wire %s", log_id(entry.wire));
+		if (entry.wirebit >= 0)
+			str += stringf(" -wirebit %d", entry.wirebit);
+		for (auto &s : entry.src)
+			str += stringf(" -src %s", s.c_str());
+		if (filename.empty())
+			log("%s\n", str.c_str());
+		else
+			fout << str << std::endl;
+	}
+}
+
+SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
+{
+	Wire *ctrl_wire = module->wire(name);
+
+	if (ctrl_wire == nullptr)
+	{
+		log("Adding ctrl port %s to module %s.\n", log_id(name), log_id(module));
+
+		ctrl_wire = module->addWire(name, width);
+		ctrl_wire->port_input = true;
+		module->fixup_ports();
+
+		for (auto mod : module->design->modules())
+		for (auto cell : mod->cells())
+		{
+			if (cell->type != module->name)
+				continue;
+
+			SigSpec ctrl = mutate_ctrl_sig(mod, name, width);
+
+			log("Connecting ctrl port to cell %s in module %s.\n", log_id(cell), log_id(mod));
+			cell->setPort(name, ctrl);
+		}
+	}
+
+	log_assert(GetSize(ctrl_wire) == width);
+	return ctrl_wire;
+}
+
+SigBit mutate_ctrl(Module *module, const mutate_opts_t &opts)
+{
+	if (opts.ctrl_name.empty())
+		return State::S1;
+
+	SigSpec sig = mutate_ctrl_sig(module, opts.ctrl_name, opts.ctrl_width);
+	return module->Eq(NEW_ID, sig, Const(opts.ctrl_value, GetSize(sig)));
+}
+
+SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec unchanged_sig, SigSpec changed_sig)
+{
+	SigBit ctrl_bit = mutate_ctrl(module, opts);
+	if (ctrl_bit == State::S0)
+		return unchanged_sig;
+	if (ctrl_bit == State::S1)
+		return changed_sig;
+	return module->Mux(NEW_ID, unchanged_sig, changed_sig, ctrl_bit);
+}
+
+void mutate_inv(Design *design, const mutate_opts_t &opts)
+{
+	Module *module = design->module(opts.module);
+	Cell *cell = module->cell(opts.cell);
+
+	SigBit bit = cell->getPort(opts.port)[opts.portbit];
+	SigBit inbit, outbit;
+
+	if (cell->input(opts.port))
+	{
+		log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
+		SigBit outbit = module->Not(NEW_ID, bit);
+		bit = mutate_ctrl_mux(module, opts, bit, outbit);
+	}
+	else
+	{
+		log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
+		SigBit inbit = module->addWire(NEW_ID);
+		SigBit outbit = module->Not(NEW_ID, inbit);
+		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
+		bit = inbit;
+	}
+
+	SigSpec s = cell->getPort(opts.port);
+	s[opts.portbit] = bit;
+	cell->setPort(opts.port, s);
+}
+
+void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
+{
+	Module *module = design->module(opts.module);
+	Cell *cell = module->cell(opts.cell);
+
+	SigBit bit = cell->getPort(opts.port)[opts.portbit];
+	SigBit inbit, outbit;
+
+	if (cell->input(opts.port))
+	{
+		log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
+		SigBit outbit = one ? State::S1 : State::S0;
+		bit = mutate_ctrl_mux(module, opts, bit, outbit);
+	}
+	else
+	{
+		log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
+		SigBit inbit = module->addWire(NEW_ID);
+		SigBit outbit = one ? State::S1 : State::S0;
+		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
+		bit = inbit;
+	}
+
+	SigSpec s = cell->getPort(opts.port);
+	s[opts.portbit] = bit;
+	cell->setPort(opts.port, s);
+}
+
+void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
+{
+	Module *module = design->module(opts.module);
+	Cell *cell = module->cell(opts.cell);
+
+	SigBit bit = cell->getPort(opts.port)[opts.portbit];
+	SigBit ctrl = cell->getPort(opts.port)[opts.ctrlbit];
+	SigBit inbit, outbit;
+
+	if (cell->input(opts.port))
+	{
+		log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
+		SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl);
+		bit = mutate_ctrl_mux(module, opts, bit, outbit);
+	}
+	else
+	{
+		log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
+		SigBit inbit = module->addWire(NEW_ID);
+		SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl);
+		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
+		bit = inbit;
+	}
+
+	SigSpec s = cell->getPort(opts.port);
+	s[opts.portbit] = bit;
+	cell->setPort(opts.port, s);
+}
+
+struct MutatePass : public Pass {
+	MutatePass() : Pass("mutate", "generate or apply design mutations") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    mutate -list N [options] [selection]\n");
+		log("\n");
+		log("Create a list of N mutations using an even sampling.\n");
+		log("\n");
+		log("    -o filename\n");
+		log("        Write list to this file instead of console output\n");
+		log("\n");
+		log("    -seed N\n");
+		log("        RNG seed for selecting mutations\n");
+		log("\n");
+		log("    -ctrl name width value\n");
+		log("        Add -ctrl options to the output. Use 'value' for first mutation, then\n");
+		log("        simply count up from there.\n");
+		log("\n");
+		log("    -mode name\n");
+		log("    -module name\n");
+		log("    -cell name\n");
+		log("    -port name\n");
+		log("    -portbit int\n");
+		log("    -ctrlbit int\n");
+		log("    -wire name\n");
+		log("    -wirebit int\n");
+		log("    -src string\n");
+		log("        Filter list of mutation candidates to those matching\n");
+		log("        the given parameters.\n");
+		log("\n");
+		log("    -cfg option int\n");
+		log("        Set a configuration option. Options available:\n");
+		log("          weight_pq_w weight_pq_b weight_pq_c weight_pq_s\n");
+		log("          weight_pq_mw weight_pq_mb weight_pq_mc weight_pq_ms\n");
+		log("          weight_cover pick_cover_prcnt\n");
+		log("\n");
+		log("\n");
+		log("    mutate -mode MODE [options]\n");
+		log("\n");
+		log("Apply the given mutation.\n");
+		log("\n");
+		log("    -ctrl name width value\n");
+		log("        Add a control signal with the given name and width. The mutation is\n");
+		log("        activated if the control signal equals the given value.\n");
+		log("\n");
+		log("    -module name\n");
+		log("    -cell name\n");
+		log("    -port name\n");
+		log("    -portbit int\n");
+		log("    -ctrlbit int\n");
+		log("        Mutation parameters, as generated by 'mutate -list N'.\n");
+		log("\n");
+		log("    -wire name\n");
+		log("    -wirebit int\n");
+		log("    -src string\n");
+		log("        Ignored. (They are generated by -list for documentation purposes.)\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		mutate_opts_t opts;
+		string filename;
+		int N = -1;
+
+		log_header(design, "Executing MUTATE pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-list" && argidx+1 < args.size()) {
+				N = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-o" && argidx+1 < args.size()) {
+				filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-seed" && argidx+1 < args.size()) {
+				opts.seed = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-mode" && argidx+1 < args.size()) {
+				opts.mode = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-ctrl" && argidx+3 < args.size()) {
+				opts.ctrl_name = RTLIL::escape_id(args[++argidx]);
+				opts.ctrl_width = atoi(args[++argidx].c_str());
+				opts.ctrl_value = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-module" && argidx+1 < args.size()) {
+				opts.module = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-cell" && argidx+1 < args.size()) {
+				opts.cell = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-port" && argidx+1 < args.size()) {
+				opts.port = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-portbit" && argidx+1 < args.size()) {
+				opts.portbit = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-ctrlbit" && argidx+1 < args.size()) {
+				opts.ctrlbit = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-wire" && argidx+1 < args.size()) {
+				opts.wire = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-wirebit" && argidx+1 < args.size()) {
+				opts.wirebit = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-src" && argidx+1 < args.size()) {
+				opts.src.insert(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-cfg" && argidx+2 < args.size()) {
+				if (args[argidx+1] == "pick_cover_prcnt") {
+					opts.pick_cover_prcnt = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_cover") {
+					opts.weight_cover = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_w") {
+					opts.weight_pq_w = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_b") {
+					opts.weight_pq_b = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_c") {
+					opts.weight_pq_c = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_s") {
+					opts.weight_pq_s = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_mw") {
+					opts.weight_pq_mw = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_mb") {
+					opts.weight_pq_mb = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_mc") {
+					opts.weight_pq_mc = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_ms") {
+					opts.weight_pq_ms = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (N >= 0) {
+			mutate_list(design, opts, filename, N);
+			return;
+		}
+
+		if (opts.mode == "inv") {
+			mutate_inv(design, opts);
+			return;
+		}
+
+		if (opts.mode == "const0" || opts.mode == "const1") {
+			mutate_const(design, opts, opts.mode == "const1");
+			return;
+		}
+
+		if (opts.mode == "cnot0" || opts.mode == "cnot1") {
+			mutate_cnot(design, opts, opts.mode == "cnot1");
+			return;
+		}
+
+		log_cmd_error("Invalid mode: %s\n", opts.mode.c_str());
+	}
+} MutatePass;
+
+PRIVATE_NAMESPACE_END