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https://github.com/YosysHQ/yosys
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Added splice command
This commit is contained in:
Clifford Wolf
parent
08aa1062b4
commit
244e8ce1f4
4 changed files with 281 additions and 0 deletions
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@ -12,4 +12,5 @@ OBJS += passes/cmds/splitnets.o
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OBJS += passes/cmds/stat.o
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OBJS += passes/cmds/setattr.o
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OBJS += passes/cmds/copy.o
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OBJS += passes/cmds/splice.o
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252
passes/cmds/splice.cc
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252
passes/cmds/splice.cc
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@ -0,0 +1,252 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#include <tuple>
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struct SpliceWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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CellTypes ct;
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SigMap sigmap;
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std::vector<RTLIL::SigBit> driven_bits;
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std::map<RTLIL::SigBit, int> driven_bits_map;
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std::set<RTLIL::SigSpec> driven_chunks;
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std::map<RTLIL::SigSpec, RTLIL::SigSpec> spliced_signals_cache;
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std::map<RTLIL::SigSpec, RTLIL::SigSpec> sliced_signals_cache;
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SpliceWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), ct(design), sigmap(module)
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{
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}
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RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig)
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{
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if (sig.width == 0 || sig.is_fully_const())
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return sig;
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if (sliced_signals_cache.count(sig))
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return sliced_signals_cache.at(sig);
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int offset = 0;
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int p = driven_bits_map.at(sig.extract(0, 1).to_single_sigbit()) - 1;
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while (driven_bits.at(p) != RTLIL::State::Sm)
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p--, offset++;
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RTLIL::SigSpec sig_a;
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for (p++; driven_bits.at(p) != RTLIL::State::Sm; p++)
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sig_a.append(driven_bits.at(p));
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RTLIL::SigSpec new_sig = sig;
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if (sig_a.width != sig.width) {
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$slice";
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cell->parameters["\\OFFSET"] = offset;
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cell->parameters["\\A_WIDTH"] = sig_a.width;
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cell->parameters["\\Y_WIDTH"] = sig.width;
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cell->connections["\\A"] = sig_a;
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cell->connections["\\Y"] = module->new_wire(sig.width, NEW_ID);
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new_sig = cell->connections["\\Y"];
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module->add(cell);
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}
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new_sig.optimize();
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sliced_signals_cache[sig] = new_sig;
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return new_sig;
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}
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RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig)
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{
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if (sig.width == 0)
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return sig;
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if (spliced_signals_cache.count(sig))
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return spliced_signals_cache.at(sig);
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int last_bit = -1;
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std::vector<RTLIL::SigSpec> chunks;
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for (auto &bit : sig.to_sigbit_vector())
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{
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if (bit.wire == NULL)
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{
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if (last_bit == 0)
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chunks.back().append(bit);
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else
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chunks.push_back(bit);
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last_bit = 0;
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continue;
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}
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if (driven_bits_map.count(bit))
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{
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int this_bit = driven_bits_map.at(bit);
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if (last_bit+1 == this_bit)
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chunks.back().append(bit);
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else
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chunks.push_back(bit);
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last_bit = this_bit;
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continue;
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}
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log(" Failed to generate spliced signal %s.\n", log_signal(sig));
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spliced_signals_cache[sig] = sig;
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return sig;
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}
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RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
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for (size_t i = 1; i < chunks.size(); i++) {
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RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$concat";
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cell->parameters["\\A_WIDTH"] = new_sig.width;
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cell->parameters["\\B_WIDTH"] = sig2.width;
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cell->connections["\\A"] = new_sig;
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cell->connections["\\B"] = sig2;
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cell->connections["\\Y"] = module->new_wire(new_sig.width + sig2.width, NEW_ID);
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new_sig = cell->connections["\\Y"];
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module->add(cell);
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}
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new_sig.optimize();
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spliced_signals_cache[sig] = new_sig;
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log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig));
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return new_sig;
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}
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void run()
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{
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log("Splicing signals in module %s:\n", RTLIL::id2cstr(module->name));
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driven_bits.push_back(RTLIL::State::Sm);
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driven_bits.push_back(RTLIL::State::Sm);
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for (auto &it : module->wires)
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if (it.second->port_input) {
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RTLIL::SigSpec sig = sigmap(it.second);
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driven_chunks.insert(sig);
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for (auto &bit : sig.to_sigbit_vector())
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driven_bits.push_back(bit);
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driven_bits.push_back(RTLIL::State::Sm);
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}
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for (auto &it : module->cells)
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for (auto &conn : it.second->connections)
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
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RTLIL::SigSpec sig = sigmap(conn.second);
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driven_chunks.insert(sig);
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for (auto &bit : sig.to_sigbit_vector())
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driven_bits.push_back(bit);
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driven_bits.push_back(RTLIL::State::Sm);
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}
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driven_bits.push_back(RTLIL::State::Sm);
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for (size_t i = 0; i < driven_bits.size(); i++)
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driven_bits_map[driven_bits[i]] = i;
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for (auto &it : module->cells) {
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if (!design->selected(module, it.second))
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continue;
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for (auto &conn : it.second->connections)
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if (ct.cell_input(it.second->type, conn.first)) {
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RTLIL::SigSpec sig = sigmap(conn.second);
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if (driven_chunks.count(sig) > 0)
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continue;
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conn.second = get_spliced_signal(sig);
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}
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}
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std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_outputs;
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for (auto &it : module->wires)
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if (it.second->port_output) {
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if (!design->selected(module, it.second))
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continue;
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RTLIL::SigSpec sig = sigmap(it.second);
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if (driven_chunks.count(sig) > 0)
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continue;
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RTLIL::SigSpec new_sig = get_spliced_signal(sig);
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if (new_sig != sig)
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rework_outputs.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, new_sig));
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}
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for (auto &it : rework_outputs)
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{
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module->wires.erase(it.first->name);
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RTLIL::Wire *new_port = new RTLIL::Wire(*it.first);
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it.first->name = NEW_ID;
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it.first->port_id = 0;
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it.first->port_input = false;
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it.first->port_output = false;
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module->add(it.first);
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module->add(new_port);
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module->connections.push_back(RTLIL::SigSig(new_port, it.second));
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}
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}
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};
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struct SplicePass : public Pass {
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SplicePass() : Pass("splice", "create explicit splicing cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splice [selection]\n");
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log("\n");
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log("This command adds $slice and $concat cells to the design to make the splicing\n");
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log("of multi-bit signals explicit. This for example is useful for coarse grain\n");
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log("synthesis, where dedidacted hardware is needed to splice signals.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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extra_args(args, 1, design);
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log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
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for (auto &mod_it : design->modules)
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{
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if (!design->selected(mod_it.second))
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continue;
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if (mod_it.second->processes.size()) {
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log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
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continue;
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}
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SpliceWorker worker(design, mod_it.second);
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worker.run();
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}
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}
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} SplicePass;
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