mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-02 12:37:53 +00:00
Code Activity

synth_gatemate: Initial implementation

Browse source 
Signed-off-by: Patrick Urban <patrick.urban@web.de>
This commit is contained in:
Patrick Urban 2021-09-13 17:16:15 +02:00 • committed by Marcelina Kościelnicka
parent b3e2001e1f
commit 240d289fff
29 changed files with 4053 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

33
tests/arch/gatemate/mul.ys Normal file
View file

@ -0,0 +1,33 @@
read_verilog mul.v
design -save read
hierarchy -top mul_plain
proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_plain # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MULT
select -assert-none t:CC_MULT %% t:* %D
design -load read
hierarchy -top mul_signed_async
proc
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_signed_async # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MULT
select -assert-count 1 t:CC_BUFG
select -assert-count 28 t:CC_DFF
select -assert-none t:CC_MULT t:CC_BUFG t:CC_DFF %% t:* %D
design -load read
hierarchy -top mul_unsigned_sync
proc
equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned_sync # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_MULT
select -assert-count 1 t:CC_BUFG
select -assert-count 18 t:CC_LUT4
select -assert-count 18 t:CC_DFF
select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D