mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-11 21:50:54 +00:00
Code Activity

synth_gatemate: Initial implementation

Browse source 
Signed-off-by: Patrick Urban <patrick.urban@web.de>
This commit is contained in:
Patrick Urban 2021-09-13 17:16:15 +02:00 • committed by Marcelina Kościelnicka
parent b3e2001e1f
commit 240d289fff
29 changed files with 4053 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

79
tests/arch/gatemate/mul.v Normal file
View file

@ -0,0 +1,79 @@
module mul_plain(a, b, p);
parameter M = 6;
parameter N = 6;
input wire [M-1:0] a;
input wire [N-1:0] b;
output wire [M+N-1:0] p;
assign p = a * b;
endmodule
module mul_signed_async (clk, rst, en, a, b, p);
parameter M = 8;
parameter N = 6;
input wire signed clk, rst, en;
input wire signed [M-1:0] a;
input wire signed [N-1:0] b;
output reg signed [M+N-1:0] p;
reg signed [M-1:0] a_reg;
reg signed [N-1:0] b_reg;
// signed M*N multiplier with
// - input and output pipeline registers
// - asynchronous reset (active high)
// - clock enable (active high)
always @(posedge clk or posedge rst)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule
module mul_unsigned_sync (clk, rst, en, a, b, p);
parameter M = 6;
parameter N = 3;
input wire clk, rst, en;
input wire [M-1:0] a;
input wire [N-1:0] b;
output reg [M+N-1:0] p;
reg [M-1:0] a_reg;
reg [N-1:0] b_reg;
// unsigned M*N multiplier with
// - input and output pipeline registers
// - synchronous reset (active high)
// - clock enable (active high)
always @(posedge clk)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule