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verific: Pass list of top modules to static elaboration

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This commit is contained in:
Jannis Harder 2023-10-05 16:28:17 +02:00
parent aeb742b8b3
commit 23b9e61c47
1 changed files with 84 additions and 63 deletions
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31
frontends/verific/verific.cc
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@ -3595,6 +3595,9 @@ struct VerificPass : public Pass {
std::set<std::string> top_mod_names; std::set<std::string> top_mod_names;
if (mode_all)
{
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite(work, &parameters); VerificExtensions::ElaborateAndRewrite(work, &parameters);
verific_error_msg.clear(); verific_error_msg.clear();
@ -3602,8 +3605,6 @@ struct VerificPass : public Pass {
if (!ppfile.empty()) if (!ppfile.empty())
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
if (mode_all)
{
log("Running hier_tree::ElaborateAll().\n"); log("Running hier_tree::ElaborateAll().\n");
VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
@ -3628,15 +3629,22 @@ struct VerificPass : public Pass {
if (argidx == GetSize(args)) if (argidx == GetSize(args))
cmd_error(args, argidx, "No top module specified.\n"); cmd_error(args, argidx, "No top module specified.\n");
Array *netlists = nullptr;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
#endif
{
VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
#endif #endif
Array veri_modules, vhdl_units; Array veri_modules, vhdl_units;
for (; argidx < GetSize(args); argidx++) for (int i = argidx; i < GetSize(args); i++)
{ {
const char *name = args[argidx].c_str(); const char *name = args[i].c_str();
top_mod_names.insert(name); top_mod_names.insert(name);
VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
@ -3677,7 +3685,18 @@ struct VerificPass : public Pass {
log_error("Can't find module/unit '%s'.\n", name); log_error("Can't find module/unit '%s'.\n", name);
} }
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, &parameters);
verific_error_msg.clear();
#endif
if (!ppfile.empty())
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
continue;
}
#endif
const char *lib_name = nullptr; const char *lib_name = nullptr;
SetIter si; SetIter si;
FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
@ -3694,7 +3713,9 @@ struct VerificPass : public Pass {
} }
log("Running hier_tree::Elaborate().\n"); log("Running hier_tree::Elaborate().\n");
Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters); netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
}
Netlist *nl; Netlist *nl;
int i; int i;