mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	alumacc: alternative cmp unification implementation
This commit is contained in:
		
							parent
							
								
									92afe26d6b
								
							
						
					
					
						commit
						23b3638c1e
					
				
					 1 changed files with 18 additions and 8 deletions
				
			
		| 
						 | 
					@ -405,11 +405,6 @@ struct AlumaccWorker
 | 
				
			||||||
			RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
 | 
								RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
 | 
				
			||||||
			RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
 | 
								RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			if (B < A && GetSize(B)) {
 | 
					 | 
				
			||||||
				cmp_less = !cmp_less;
 | 
					 | 
				
			||||||
				std::swap(A, B);
 | 
					 | 
				
			||||||
			}
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
			alunode_t *n = nullptr;
 | 
								alunode_t *n = nullptr;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			for (auto node : sig_alu[RTLIL::SigSig(A, B)])
 | 
								for (auto node : sig_alu[RTLIL::SigSig(A, B)])
 | 
				
			||||||
| 
						 | 
					@ -418,6 +413,16 @@ struct AlumaccWorker
 | 
				
			||||||
					break;
 | 
										break;
 | 
				
			||||||
				}
 | 
									}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								if (n == nullptr) {
 | 
				
			||||||
 | 
									for (auto node : sig_alu[RTLIL::SigSig(B, A)])
 | 
				
			||||||
 | 
										if (node->invert_b && node->c == State::S1) {
 | 
				
			||||||
 | 
											n = node;
 | 
				
			||||||
 | 
											cmp_less = !cmp_less;
 | 
				
			||||||
 | 
											std::swap(A, B);
 | 
				
			||||||
 | 
											break;
 | 
				
			||||||
 | 
										}
 | 
				
			||||||
 | 
								}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			if (n == nullptr) {
 | 
								if (n == nullptr) {
 | 
				
			||||||
				n = new alunode_t;
 | 
									n = new alunode_t;
 | 
				
			||||||
				n->a = A;
 | 
									n->a = A;
 | 
				
			||||||
| 
						 | 
					@ -445,9 +450,6 @@ struct AlumaccWorker
 | 
				
			||||||
			RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
 | 
								RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
 | 
				
			||||||
			RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
 | 
								RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			if (B < A && GetSize(B))
 | 
					 | 
				
			||||||
				std::swap(A, B);
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
			alunode_t *n = nullptr;
 | 
								alunode_t *n = nullptr;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			for (auto node : sig_alu[RTLIL::SigSig(A, B)])
 | 
								for (auto node : sig_alu[RTLIL::SigSig(A, B)])
 | 
				
			||||||
| 
						 | 
					@ -456,6 +458,14 @@ struct AlumaccWorker
 | 
				
			||||||
					break;
 | 
										break;
 | 
				
			||||||
				}
 | 
									}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								if (n == nullptr) {
 | 
				
			||||||
 | 
									for (auto node : sig_alu[RTLIL::SigSig(B, A)])
 | 
				
			||||||
 | 
										if (node->invert_b && node->c == State::S1) {
 | 
				
			||||||
 | 
											n = node;
 | 
				
			||||||
 | 
											break;
 | 
				
			||||||
 | 
										}
 | 
				
			||||||
 | 
								}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			if (n != nullptr) {
 | 
								if (n != nullptr) {
 | 
				
			||||||
				log("  creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
 | 
									log("  creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
 | 
				
			||||||
				n->cells.push_back(cell);
 | 
									n->cells.push_back(cell);
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue