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Fixed handling of transparent bram rd ports on ROMs

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This commit is contained in:
Clifford Wolf 2016-08-27 17:06:22 +02:00
parent adcda6817e
commit 23afeadb5e
2 changed files with 4 additions and 0 deletions
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1
kernel/rtlil.cc
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@ -1482,6 +1482,7 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn)
log_backtrace("-X- ", yosys_xtrace-1); log_backtrace("-X- ", yosys_xtrace-1);
} }
log_assert(GetSize(conn.first) == GetSize(conn.second));
connections_.push_back(conn); connections_.push_back(conn);
} }

3
passes/memory/memory_bram.cc
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@ -656,6 +656,9 @@ grow_read_ports:;
bool transp = rd_transp[cell_port_i] == State::S1; bool transp = rd_transp[cell_port_i] == State::S1;
SigBit clksig = rd_clk[cell_port_i]; SigBit clksig = rd_clk[cell_port_i];
if (wr_ports == 0)
transp = false;
pair<SigBit, bool> clkdom(clksig, clkpol); pair<SigBit, bool> clkdom(clksig, clkpol);
if (!clken) if (!clken)
clkdom = pair<SigBit, bool>(State::S1, false); clkdom = pair<SigBit, bool>(State::S1, false);