mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Fixed handling of transparent bram rd ports on ROMs

Browse source
This commit is contained in:
Clifford Wolf 2016-08-27 17:06:22 +02:00
parent adcda6817e
commit 23afeadb5e
2 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/memory/memory_bram.cc
View file

@ -656,6 +656,9 @@ grow_read_ports:;
bool transp = rd_transp[cell_port_i] == State::S1;
SigBit clksig = rd_clk[cell_port_i];
if (wr_ports == 0)
transp = false;
pair<SigBit, bool> clkdom(clksig, clkpol);
if (!clken)
clkdom = pair<SigBit, bool>(State::S1, false);