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Added support for shifter cells to SAT generator

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Clifford Wolf 2013-06-08 15:12:08 +02:00
parent 92f04eab10
commit 23a7973094
3 changed files with 43 additions and 10 deletions
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passes/sat/example.ys
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@ -2,4 +2,5 @@ read_verilog example.v
proc; opt_clean
sat_solve -set y 1'b1 example001
sat_solve -set y 1'b1 example002
sat_solve -set y 1'b1 example003
sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
sat_solve -set y 1'b1 example004