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design.cc: Fix selections when copying

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Use `Design::selected_modules()` directly, popping at the end instead of copying the selection.
Also default to a complete selection so that boxes work as before.
Simplify to using `RTLIL::SELECT_WHOLE_CMDERR` instead of doing it manually.
Also add tests for importing selections with boxes.
This commit is contained in:
Krystine Sherwin 2025-04-08 16:35:12 +12:00
parent 911a3ae759
commit 237e454131
No known key found for this signature in database
2 changed files with 35 additions and 11 deletions
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17
passes/cmds/design.cc
View file

@ -213,22 +213,15 @@ struct DesignPass : public Pass {
if (copy_from_design != design && argidx == args.size() && !import_mode) if (copy_from_design != design && argidx == args.size() && !import_mode)
cmd_error(args, argidx, "Missing selection."); cmd_error(args, argidx, "Missing selection.");
RTLIL::Selection sel;
if (argidx != args.size()) { if (argidx != args.size()) {
handle_extra_select_args(this, args, argidx, args.size(), copy_from_design); handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
sel = copy_from_design->selection();
copy_from_design->pop_selection();
argidx = args.size(); argidx = args.size();
} else {
copy_from_design->push_complete_selection();
} }
for (auto mod : copy_from_design->modules()) { for (auto mod : copy_from_design->selected_modules(RTLIL::SELECT_WHOLE_CMDERR, RTLIL::SB_ALL))
if (sel.selected_whole_module(mod->name)) { copy_src_modules.push_back(mod);
copy_src_modules.push_back(mod);
continue;
}
if (sel.selected_module(mod->name))
log_cmd_error("Module %s is only partly selected.\n", log_id(mod->name));
}
if (import_mode) { if (import_mode) {
std::vector<RTLIL::Module*> candidates; std::vector<RTLIL::Module*> candidates;
@ -246,6 +239,8 @@ struct DesignPass : public Pass {
if (GetSize(candidates) == 1) if (GetSize(candidates) == 1)
copy_src_modules = std::move(candidates); copy_src_modules = std::move(candidates);
} }
copy_from_design->pop_selection();
} }
extra_args(args, argidx, design, false); extra_args(args, argidx, design, false);

29
tests/select/boxes_import.ys Normal file
View file

@ -0,0 +1,29 @@
read_verilog -specify boxes.v
design -save read
logger -expect-no-warnings
delete =bb %n
select -assert-mod-count 1 =*
design -stash just_bb
design -import just_bb
select -assert-mod-count 0 *
select -assert-mod-count 1 =*
design -reset
design -import just_bb -as new
select -assert-mod-count 0 *
select -assert-mod-count 1 =*
design -reset
design -import read -as new_top top
design -import read -as new_bb =bb
select -assert-mod-count 1 *
select -assert-mod-count 2 =*
logger -check-expected
logger -expect warning "Selection .wb. did not match any module\." 1
logger -expect error "No top module found in source design\." 1
design -import read -as new_wb wb