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script added

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This commit is contained in:
Ahmed Irfan 2014-01-18 21:54:52 +01:00
parent 90483f489b
commit 234d0d0e1c
2 changed files with 28 additions and 9 deletions
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11
btor.ys
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@ -1,10 +1,3 @@
#design should be loaded before executing
#set the: hierarchy -top <module_top>
#set the: hierarchy -libdir <dir>
#high level synthesis
#################
#converting processes to cells
proc; proc;
opt; opt_const -mux_undef; opt; opt; opt_const -mux_undef; opt;
rename -hide;;; rename -hide;;;
@ -17,6 +10,6 @@ flatten;;
memory_unpack; memory_unpack;
#cell output to be a single wire #cell output to be a single wire
splitnets -driver; splitnets -driver;
setundef -zero -undriven;
opt;;; opt;;;
#writing btor
write_btor design.btor;

26
verilog2btor.sh Executable file
View file

@ -0,0 +1,26 @@
#!/bin/sh
#
# Script to writing btor from verilog design
#
if [ "$#" -ne 3 ]; then
echo "Usage: $0 input.v output.btor top-module-name" >&2
exit 1
fi
if ! [ -e "$1" ]; then
echo "$1 not found" >&2
exit 1
fi
FULL_PATH=$(readlink -f $1)
DIR=$(dirname $FULL_PATH)
./yosys -p "
read_verilog $1;
hierarchy -top $3;
hierarchy -libdir $DIR;
hierarchy -check;
script btor.ys;
write_btor $2;"