mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00
Code Activity

Instantiate cell type (from sym file) otherwise 'clean' warnings

Browse source
This commit is contained in:
Eddie Hung 2019-05-27 12:16:10 -07:00
parent 03b289a851
commit 234156c01a
3 changed files with 15 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

9
frontends/aiger/aigerparse.cc
View file

@ -720,14 +720,17 @@ void AigerReader::post_process()
}
else log_abort();
std::string port;
mf >> port;
std::string port, type;
mf >> port >> type;
RTLIL::IdString cell_name = RTLIL::escape_id(symbol);
RTLIL::IdString cell_port = RTLIL::escape_id(port);
RTLIL::IdString cell_type = RTLIL::escape_id(type);
RTLIL::Cell* cell = module->cell(cell_name);
if (!cell)
cell = module->addCell(cell_name, "$__blackbox__");
cell = module->addCell(cell_name, cell_type);
else
log_assert(cell->type == cell_type);
wire->port_input = false;
wire->port_output = false;
if (cell->hasPort(cell_port)) {