3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00

Instantiate cell type (from sym file) otherwise 'clean' warnings

This commit is contained in:
Eddie Hung 2019-05-27 12:16:10 -07:00
parent 03b289a851
commit 234156c01a
3 changed files with 15 additions and 12 deletions

View file

@ -879,13 +879,15 @@ struct XAigerWriter
int i = std::get<3>(c);
int a = bit2aig(b);
log_assert((a & 1) == 0);
input_lines[a] += stringf("cinput %d %d %s %s\n", (a >> 1)-1, i, log_id(std::get<1>(c)), log_id(std::get<2>(c)));
RTLIL::Cell* cell = std::get<1>(c);
input_lines[a] += stringf("cinput %d %d %s %s %s\n", (a >> 1)-1, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type));
}
for (const auto &c : co_bits) {
int i = std::get<3>(c);
int o = std::get<4>(c);
output_lines[o] += stringf("coutput %d %d %s %s\n", o, i, log_id(std::get<1>(c)), log_id(std::get<2>(c)));
RTLIL::Cell* cell = std::get<1>(c);
output_lines[o] += stringf("coutput %d %d %s %s %s\n", o, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type));
}
input_lines.sort();