mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Do not treat $__ABC_FF_ as a user cell

Browse source
This commit is contained in:
Eddie Hung 2019-06-15 19:36:55 -07:00
parent 9ec57b46c2
commit 2309459605
2 changed files with 15 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

18
backends/aiger/xaiger.cc
View file

@ -222,15 +222,15 @@ struct XAigerWriter
log_assert(!holes_mode);
// FIXME: Should short here, rather than provide $__ABC_FF_
// to ABC like a user cell
//if (cell->type == "$__ABC_FF_")
//{
// SigBit D = sigmap(cell->getPort("\\D").as_bit());
// SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
// alias_map[Q] = D;
// continue;
//}
if (cell->type == "$__ABC_FF_")
{
SigBit D = sigmap(cell->getPort("\\D").as_bit());
SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
continue;
}
RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;