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Add support for SVA labels in read_verilog

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-03-07 11:17:32 -08:00
parent cda37830b0
commit 22ff60850e
3 changed files with 89 additions and 26 deletions
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1
frontends/ast/simplify.cc
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@ -1511,6 +1511,7 @@ skip_dynamic_range_lvalue_expansion:;
newNode->children.push_back(assign_en);
AstNode *assertnode = new AstNode(type);
assertnode->str = str;
assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
assertnode->children[0]->str = id_check;