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Modifications of tests as per Eddie's request

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diego 2020-04-20 12:45:35 -05:00
parent 50581d5a94
commit 22f440506b
15 changed files with 1237 additions and 78 deletions
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19
tests/arch/common/dynamic_part_select/forloop_select.v
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@ -1,19 +0,0 @@
module forloop_select #(parameter WIDTH=256, SELW=4)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input en,
output reg [WIDTH-1:0] dout);
reg [SELW-1:0] sel;
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk)
begin
if (en) begin
for (sel = 0; sel < 4'hf; sel=sel+1'b1)
dout[(ctrl*sel)+:SLICE] <= din;
end
end
endmodule

59
tests/arch/xilinx/dynamic_part_select.ys
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@ -1,59 +0,0 @@
#### Original testcase ###
read_verilog ../common/dynamic_part_select/original.v
hierarchy -top original
prep -flatten -top original
design -save gold
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter
### Multiple blocking assingments ###
read_verilog ../common/dynamic_part_select/multiple_blocking.v
hierarchy -top multiple_blocking
prep -flatten -top multiple_blocking
design -save gold
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter
### Non-blocking to the same output register ###
read_verilog ../common/dynamic_part_select/nonblocking.v
hierarchy -top nonblocking
prep -flatten -top nonblocking
design -save gold
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter
### For-loop select, one dynamic input
read_verilog ../common/dynamic_part_select/forloop_select.v
hierarchy -top forloop_select
prep -flatten -top forloop_select
design -save gold
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -seq 5 -prove-skip 1 miter
### Double loop (part-select, reset) ###
read_verilog ../common/dynamic_part_select/reset_test.v
hierarchy -top reset_test
prep -flatten -top reset_test
design -save gold
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -seq 10 -prove-skip 1 miter
### Reversed part-select case ###
read_verilog ../common/dynamic_part_select/reversed.v
hierarchy -top reversed
prep -flatten -top reversed
design -save gold
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -seq 20 -prove-skip 1 miter

119
tests/various/dynamic_part_select.ys Normal file
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@ -0,0 +1,119 @@
### Original testcase ###
read_verilog ./dynamic_part_select/original.v
hierarchy -top original; proc; opt;
prep -flatten -top original
rename -top gold
design -stash gold
read_verilog ./dynamic_part_select/original_gate.v
hierarchy -top original_gate; proc; opt;
prep -flatten -top original_gate
rename -top gate
design -stash gate
design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### Multiple blocking assingments ###
read_verilog ./dynamic_part_select/multiple_blocking.v
hierarchy -top multiple_blocking; proc; opt;
prep -flatten -top multiple_blocking
rename -top gold
design -stash gold
read_verilog ./dynamic_part_select/multiple_blocking_gate.v
hierarchy -top multiple_blocking_gate; proc; opt;
prep -flatten -top multiple_blocking_gate
rename -top gate
design -stash gate
design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### Non-blocking to the same output register ###
read_verilog ./dynamic_part_select/nonblocking.v
hierarchy -top nonblocking; proc; opt;
prep -flatten -top nonblocking
rename -top gold
design -stash gold
read_verilog ./dynamic_part_select/nonblocking_gate.v
hierarchy -top nonblocking_gate; proc; opt;
prep -flatten -top nonblocking_gate
rename -top gate
design -stash gate
design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### For-loop select, one dynamic input
read_verilog ./dynamic_part_select/forloop_select.v
hierarchy -top forloop_select; proc; opt;
prep -flatten -top forloop_select
rename -top gold
design -stash gold
read_verilog ./dynamic_part_select/forloop_select_gate.v
hierarchy -top forloop_select_gate; proc; opt;
prep -flatten -top forloop_select_gate
rename -top gate
design -stash gate
design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
#### Double loop (part-select, reset) ###
read_verilog ./dynamic_part_select/reset_test.v
hierarchy -top reset_test; proc; opt;
prep -flatten -top reset_test
rename -top gold
design -stash gold
read_verilog ./dynamic_part_select/reset_test_gate.v
hierarchy -top reset_test_gate; proc; opt;
prep -flatten -top reset_test_gate
rename -top gate
design -stash gate
design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### Reversed part-select case ###
read_verilog ./dynamic_part_select/reversed.v
hierarchy -top reversed; proc; opt;
prep -flatten -top reversed
rename -top gold
design -stash gold
read_verilog ./dynamic_part_select/reversed_gate.v
hierarchy -top reversed_gate; proc; opt;
prep -flatten -top reversed_gate
rename -top gate
design -stash gate
design -copy-from gold -as gold gold
design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv

19
tests/various/dynamic_part_select/forloop_select.v Normal file
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@ -0,0 +1,19 @@
module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
(input clk,
input [CTRLW-1:0] ctrl,
input [DINW-1:0] din,
input en,
output reg [WIDTH-1:0] dout);
reg [SELW:0] sel;
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk)
begin
if (en) begin
for (sel = 0; sel <= 4'hf; sel=sel+1'b1)
dout[(ctrl*sel)+:SLICE] <= din;
end
end
endmodule

559
tests/various/dynamic_part_select/forloop_select_gate.v Normal file
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@ -0,0 +1,559 @@
module forloop_select_gate (clk, ctrl, din, en, dout);
input clk;
input [3:0] ctrl;
input [15:0] din;
input en;
output reg [15:0] dout;
reg [4:0] sel;
always @(posedge clk)
case (|(en))
1'b 1:
begin
case (({(ctrl)*(0)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 00001)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 00010)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 00011)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 00100)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 00101)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 00110)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 00111)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01000)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01001)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01010)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01011)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01100)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01101)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01110)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
case (({(ctrl)*(5'b 01111)})+(0))
0:
dout[0:0] <= din;
1:
dout[1:1] <= din;
2:
dout[2:2] <= din;
3:
dout[3:3] <= din;
4:
dout[4:4] <= din;
5:
dout[5:5] <= din;
6:
dout[6:6] <= din;
7:
dout[7:7] <= din;
8:
dout[8:8] <= din;
9:
dout[9:9] <= din;
10:
dout[10:10] <= din;
11:
dout[11:11] <= din;
12:
dout[12:12] <= din;
13:
dout[13:13] <= din;
14:
dout[14:14] <= din;
15:
dout[15:15] <= din;
endcase
sel = 5'b 10000;
end
endcase
endmodule

19
tests/various/dynamic_part_select/multiple_blocking.v Normal file
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@ -0,0 +1,19 @@
module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
(input clk,
input [CTRLW-1:0] ctrl,
input [DINW-1:0] din,
input [SELW-1:0] sel,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
reg [CTRLW:0] a;
reg [SELW-1:0] b;
reg [DINW:0] c;
always @(posedge clk) begin
a = ctrl + 1;
b = sel - 1;
c = ~din;
dout = dout + 1;
dout[a*b+:SLICE] = c;
end
endmodule

83
tests/various/dynamic_part_select/multiple_blocking_gate.v Normal file
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@ -0,0 +1,83 @@
module multiple_blocking_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [1:0] din;
input [0:0] sel;
output reg [31:0] dout;
reg [5:0] a;
reg [0:0] b;
reg [2:0] c;
always @(posedge clk)
begin
a = (ctrl)+(1);
b = (sel)-(1);
c = ~(din);
dout = (dout)+(1);
case (({(a)*(b)})+(0))
0:
dout[31:0] = c;
1:
dout[31:1] = c;
2:
dout[31:2] = c;
3:
dout[31:3] = c;
4:
dout[31:4] = c;
5:
dout[31:5] = c;
6:
dout[31:6] = c;
7:
dout[31:7] = c;
8:
dout[31:8] = c;
9:
dout[31:9] = c;
10:
dout[31:10] = c;
11:
dout[31:11] = c;
12:
dout[31:12] = c;
13:
dout[31:13] = c;
14:
dout[31:14] = c;
15:
dout[31:15] = c;
16:
dout[31:16] = c;
17:
dout[31:17] = c;
18:
dout[31:18] = c;
19:
dout[31:19] = c;
20:
dout[31:20] = c;
21:
dout[31:21] = c;
22:
dout[31:22] = c;
23:
dout[31:23] = c;
24:
dout[31:24] = c;
25:
dout[31:25] = c;
26:
dout[31:26] = c;
27:
dout[31:27] = c;
28:
dout[31:28] = c;
29:
dout[31:29] = c;
30:
dout[31:30] = c;
31:
dout[31:31] = c;
endcase
end
endmodule

14
tests/various/dynamic_part_select/nonblocking.v Normal file
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@ -0,0 +1,14 @@
module nonblocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
(input clk,
input [CTRLW-1:0] ctrl,
input [DINW-1:0] din,
input [SELW-1:0] sel,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk) begin
dout <= dout + 1;
dout[ctrl*sel+:SLICE] <= din ;
end
endmodule

77
tests/various/dynamic_part_select/nonblocking_gate.v Normal file
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module nonblocking_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [1:0] din;
input [0:0] sel;
output reg [31:0] dout;
always @(posedge clk)
begin
dout <= (dout)+(1);
case (({(ctrl)*(sel)})+(0))
0:
dout[31:0] <= din;
1:
dout[31:1] <= din;
2:
dout[31:2] <= din;
3:
dout[31:3] <= din;
4:
dout[31:4] <= din;
5:
dout[31:5] <= din;
6:
dout[31:6] <= din;
7:
dout[31:7] <= din;
8:
dout[31:8] <= din;
9:
dout[31:9] <= din;
10:
dout[31:10] <= din;
11:
dout[31:11] <= din;
12:
dout[31:12] <= din;
13:
dout[31:13] <= din;
14:
dout[31:14] <= din;
15:
dout[31:15] <= din;
16:
dout[31:16] <= din;
17:
dout[31:17] <= din;
18:
dout[31:18] <= din;
19:
dout[31:19] <= din;
20:
dout[31:20] <= din;
21:
dout[31:21] <= din;
22:
dout[31:22] <= din;
23:
dout[31:23] <= din;
24:
dout[31:24] <= din;
25:
dout[31:25] <= din;
26:
dout[31:26] <= din;
27:
dout[31:27] <= din;
28:
dout[31:28] <= din;
29:
dout[31:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
end
endmodule

12
tests/various/dynamic_part_select/original.v Normal file
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@ -0,0 +1,12 @@
module original #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
(input clk,
input [CTRLW-1:0] ctrl,
input [DINW-1:0] din,
input [SELW-1:0] sel,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk)
begin
dout[ctrl*sel+:SLICE] <= din ;
end
endmodule

74
tests/various/dynamic_part_select/original_gate.v Normal file
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@ -0,0 +1,74 @@
module original_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [1:0] din;
input [0:0] sel;
output reg [31:0] dout;
always @(posedge clk)
case (({(ctrl)*(sel)})+(0))
0:
dout[31:0] <= din;
1:
dout[31:1] <= din;
2:
dout[31:2] <= din;
3:
dout[31:3] <= din;
4:
dout[31:4] <= din;
5:
dout[31:5] <= din;
6:
dout[31:6] <= din;
7:
dout[31:7] <= din;
8:
dout[31:8] <= din;
9:
dout[31:9] <= din;
10:
dout[31:10] <= din;
11:
dout[31:11] <= din;
12:
dout[31:12] <= din;
13:
dout[31:13] <= din;
14:
dout[31:14] <= din;
15:
dout[31:15] <= din;
16:
dout[31:16] <= din;
17:
dout[31:17] <= din;
18:
dout[31:18] <= din;
19:
dout[31:19] <= din;
20:
dout[31:20] <= din;
21:
dout[31:21] <= din;
22:
dout[31:22] <= din;
23:
dout[31:23] <= din;
24:
dout[31:24] <= din;
25:
dout[31:25] <= din;
26:
dout[31:26] <= din;
27:
dout[31:27] <= din;
28:
dout[31:28] <= din;
29:
dout[31:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
endmodule

23
tests/various/dynamic_part_select/reset_test.v Normal file
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@ -0,0 +1,23 @@
module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
(input clk,
input [CTRLW-1:0] ctrl,
input [DINW-1:0] din,
input [SELW-1:0] sel,
output reg [WIDTH-1:0] dout);
reg [SELW:0] i;
wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}};
localparam SLICE = WIDTH/(SELW**2);
// Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for
// whatever reason.
always @(posedge clk) begin
if (reset) begin: reset_mask
for (i = 0; i < {SELW{1'b1}}; i=i+1) begin
dout[i*rval+:SLICE] <= 32'hDEAD;
end
end
//else begin
dout[ctrl*sel+:SLICE] <= din;
//end
end
endmodule

151
tests/various/dynamic_part_select/reset_test_gate.v Normal file
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@ -0,0 +1,151 @@
module reset_test_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [1:0] din;
input [0:0] sel;
output reg [31:0] dout;
reg [1:0] i;
wire [0:0] rval;
assign rval = {reset, 1'b0 };
always @(posedge clk)
begin
case (|(reset))
1'b 1:
begin
case (({(0)*(rval)})+(0))
0:
dout[31:0] <= 57005;
1:
dout[31:1] <= 57005;
2:
dout[31:2] <= 57005;
3:
dout[31:3] <= 57005;
4:
dout[31:4] <= 57005;
5:
dout[31:5] <= 57005;
6:
dout[31:6] <= 57005;
7:
dout[31:7] <= 57005;
8:
dout[31:8] <= 57005;
9:
dout[31:9] <= 57005;
10:
dout[31:10] <= 57005;
11:
dout[31:11] <= 57005;
12:
dout[31:12] <= 57005;
13:
dout[31:13] <= 57005;
14:
dout[31:14] <= 57005;
15:
dout[31:15] <= 57005;
16:
dout[31:16] <= 57005;
17:
dout[31:17] <= 57005;
18:
dout[31:18] <= 57005;
19:
dout[31:19] <= 57005;
20:
dout[31:20] <= 57005;
21:
dout[31:21] <= 57005;
22:
dout[31:22] <= 57005;
23:
dout[31:23] <= 57005;
24:
dout[31:24] <= 57005;
25:
dout[31:25] <= 57005;
26:
dout[31:26] <= 57005;
27:
dout[31:27] <= 57005;
28:
dout[31:28] <= 57005;
29:
dout[31:29] <= 57005;
30:
dout[31:30] <= 57005;
31:
dout[31:31] <= 57005;
endcase
i = 1;
end
endcase
case (({(ctrl)*(sel)})+(0))
0:
dout[31:0] <= din;
1:
dout[31:1] <= din;
2:
dout[31:2] <= din;
3:
dout[31:3] <= din;
4:
dout[31:4] <= din;
5:
dout[31:5] <= din;
6:
dout[31:6] <= din;
7:
dout[31:7] <= din;
8:
dout[31:8] <= din;
9:
dout[31:9] <= din;
10:
dout[31:10] <= din;
11:
dout[31:11] <= din;
12:
dout[31:12] <= din;
13:
dout[31:13] <= din;
14:
dout[31:14] <= din;
15:
dout[31:15] <= din;
16:
dout[31:16] <= din;
17:
dout[31:17] <= din;
18:
dout[31:18] <= din;
19:
dout[31:19] <= din;
20:
dout[31:20] <= din;
21:
dout[31:21] <= din;
22:
dout[31:22] <= din;
23:
dout[31:23] <= din;
24:
dout[31:24] <= din;
25:
dout[31:25] <= din;
26:
dout[31:26] <= din;
27:
dout[31:27] <= din;
28:
dout[31:28] <= din;
29:
dout[31:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
end
endmodule

13
tests/various/dynamic_part_select/reversed.v Normal file
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@ -0,0 +1,13 @@
module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
(input clk,
input [CTRLW-1:0] ctrl,
input [DINW-1:0] din,
input [SELW-1:0] sel,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk) begin
dout[(WIDTH-ctrl*sel)-:SLICE] <= din;
end
endmodule

74
tests/various/dynamic_part_select/reversed_gate.v Normal file
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@ -0,0 +1,74 @@
module reversed_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [15:0] din;
input [3:0] sel;
output reg [31:0] dout;
always @(posedge clk)
case ((({(32)-((ctrl)*(sel))})+(1))-(2))
0:
dout[1:0] <= din;
1:
dout[2:1] <= din;
2:
dout[3:2] <= din;
3:
dout[4:3] <= din;
4:
dout[5:4] <= din;
5:
dout[6:5] <= din;
6:
dout[7:6] <= din;
7:
dout[8:7] <= din;
8:
dout[9:8] <= din;
9:
dout[10:9] <= din;
10:
dout[11:10] <= din;
11:
dout[12:11] <= din;
12:
dout[13:12] <= din;
13:
dout[14:13] <= din;
14:
dout[15:14] <= din;
15:
dout[16:15] <= din;
16:
dout[17:16] <= din;
17:
dout[18:17] <= din;
18:
dout[19:18] <= din;
19:
dout[20:19] <= din;
20:
dout[21:20] <= din;
21:
dout[22:21] <= din;
22:
dout[23:22] <= din;
23:
dout[24:23] <= din;
24:
dout[25:24] <= din;
25:
dout[26:25] <= din;
26:
dout[27:26] <= din;
27:
dout[28:27] <= din;
28:
dout[29:28] <= din;
29:
dout[30:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
endmodule