mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-28 19:35:53 +00:00
Modifications of tests as per Eddie's request
This commit is contained in:
parent
50581d5a94
commit
22f440506b
15 changed files with 1237 additions and 78 deletions
23
tests/various/dynamic_part_select/reset_test.v
Normal file
23
tests/various/dynamic_part_select/reset_test.v
Normal file
|
@ -0,0 +1,23 @@
|
|||
module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
|
||||
(input clk,
|
||||
input [CTRLW-1:0] ctrl,
|
||||
input [DINW-1:0] din,
|
||||
input [SELW-1:0] sel,
|
||||
output reg [WIDTH-1:0] dout);
|
||||
|
||||
reg [SELW:0] i;
|
||||
wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}};
|
||||
localparam SLICE = WIDTH/(SELW**2);
|
||||
// Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for
|
||||
// whatever reason.
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin: reset_mask
|
||||
for (i = 0; i < {SELW{1'b1}}; i=i+1) begin
|
||||
dout[i*rval+:SLICE] <= 32'hDEAD;
|
||||
end
|
||||
end
|
||||
//else begin
|
||||
dout[ctrl*sel+:SLICE] <= din;
|
||||
//end
|
||||
end
|
||||
endmodule
|
Loading…
Add table
Add a link
Reference in a new issue