mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-18 17:22:17 +00:00
Code Activity

Modifications of tests as per Eddie's request

Browse source
This commit is contained in:
diego 2020-04-20 12:45:35 -05:00
parent 50581d5a94
commit 22f440506b
15 changed files with 1237 additions and 78 deletions
Download patch file Download diff file Expand all files Collapse all files

19
tests/arch/common/dynamic_part_select/forloop_select.v
View file

@ -1,19 +0,0 @@
module forloop_select #(parameter WIDTH=256, SELW=4)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input en,
output reg [WIDTH-1:0] dout);
reg [SELW-1:0] sel;
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk)
begin
if (en) begin
for (sel = 0; sel < 4'hf; sel=sel+1'b1)
dout[(ctrl*sel)+:SLICE] <= din;
end
end
endmodule