mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

liberty: Support for IO liberty files for verification

Browse source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2024-06-10 16:29:11 +02:00 • committed by myrtle
parent ede3750a6c
commit 22d8df1e7e
1 changed files with 28 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

20
frontends/liberty/liberty.cc
View file

@ -214,6 +214,18 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
return stack.back().sig; return stack.back().sig;
} }
static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func, const char *three_state_expr)
{
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
cell->setParam(ID::WIDTH, GetSize(func));
cell->setPort(ID::A, func);
cell->setPort(ID::EN, create_inv_cell(module, three_state));
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
}
static void create_ff(RTLIL::Module *module, LibertyAst *node) static void create_ff(RTLIL::Module *module, LibertyAst *node)
{ {
RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0)))); RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
@ -695,6 +707,7 @@ struct LibertyFrontend : public Frontend {
LibertyAst *func = node->find("function"); LibertyAst *func = node->find("function");
if (func == NULL) if (func == NULL)
{ {
if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
if (!flag_ignore_miss_func) if (!flag_ignore_miss_func)
{ {
log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name)); log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
@ -704,11 +717,16 @@ struct LibertyFrontend : public Frontend {
goto skip_cell; goto skip_cell;
} }
} }
} else {
RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str()); RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
LibertyAst *three_state = node->find("three_state");
if (three_state) {
out_sig = create_tristate(module, out_sig, three_state->value.c_str());
}
module->connect(RTLIL::SigSig(wire, out_sig)); module->connect(RTLIL::SigSig(wire, out_sig));
} }
} }
}
module->fixup_ports(); module->fixup_ports();
design->add(module); design->add(module);