quicklogic: Test TDP36K inference with initial data

techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v

@@ -178,6 +178,7 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
 
 (* is_inferred = 1 *)
 (* is_split = 0 *)
+(* was_split_candidate = OPTION_SPLIT *)
 (* port_a_width = PORT_A_WIDTH *)
 (* port_b_width = PORT_B_WIDTH *)
 TDP36K #(

tests/arch/quicklogic/qlf_k6n10f/meminit.v

@@ -0,0 +1,50 @@
+module top(clk);
+parameter DEPTH_LOG2 = 10;
+parameter WIDTH = 36;
+parameter PRIME = 237481091;
+localparam DEPTH = 2**DEPTH_LOG2;
+
+input wire clk;
+
+(* syn_ramstyle = "block_ram" *)
+reg [WIDTH-1:0] mem [DEPTH-1:0];
+
+integer i;
+initial begin
+    for (i = 0; i < DEPTH; i = i + 1) begin
+        // Make up data by multiplying a large prime with the address,
+        // then cropping and retaining the lower bits
+        mem[i] = PRIME * i;
+    end
+end
+
+reg [DEPTH_LOG2-1:0] counter = 0;
+reg done = 1'b0;
+
+reg did_read = 1'b0;
+reg [DEPTH_LOG2-1:0] read_addr;
+reg [WIDTH-1:0] read_val;
+
+always @(posedge clk) begin
+    if (!done) begin
+        did_read <= 1'b1;
+        read_addr <= counter;
+        read_val <= mem[counter];
+    end else begin
+        did_read <= 1'b0; 
+    end
+
+    if (!done)
+        counter = counter + 1;
+    if (counter == 0)
+        done = 1;
+end
+
+wire [WIDTH-1:0] expect_val = PRIME * read_addr;
+always @(posedge clk) begin
+    if (did_read) begin
+        $display("addr %x expected %x actual %x", read_addr, expect_val, read_val);
+        assert(read_val == expect_val);
+    end
+end
+endmodule

tests/arch/quicklogic/qlf_k6n10f/meminit.ys

@@ -0,0 +1,14 @@
+read_verilog -sv meminit.v
+chparam -set DEPTH_LOG2 3 -set WIDTH 36
+prep
+opt_dff
+prep -rdff
+synth_quicklogic -family qlf_k6n10f -run map_bram:map_bram
+select -assert-none t:$mem_v2 t:$mem
+select -assert-count 1 t:TDP36K
+select -assert-count 1 t:TDP36K a:is_split=0 %i
+select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i
+read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+prep
+hierarchy -top top
+sim -assert -q -n 12 -clock clk