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Xilinx DRAMS: RAM64X1D, RAM128X1D

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Clifford Wolf 2015-04-09 13:37:07 +02:00
parent 25781e329b
commit 229825e1b8
3 changed files with 67 additions and 13 deletions
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19
techlibs/xilinx/drams_bb.v
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@ -1,11 +1,20 @@
module RAM32X1D (
module RAM64X1D (
output DPO, SPO,
input A0, A1, A2, A3, A4, D,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
input WCLK, WE
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 32'h0;
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule