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Xilinx DRAMS: RAM64X1D, RAM128X1D

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This commit is contained in:
Clifford Wolf 2015-04-09 13:37:07 +02:00
parent 25781e329b
commit 229825e1b8
3 changed files with 67 additions and 13 deletions
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23
techlibs/xilinx/drams.txt
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@ -1,7 +1,7 @@
bram $__XILINX_RAM32X1D
bram $__XILINX_RAM64X1D
init 1
abits 5
abits 6
dbits 1
groups 2
ports 1 1
@ -12,6 +12,23 @@ bram $__XILINX_RAM32X1D
clkpol 0 2
endbram
match $__XILINX_RAM32X1D
bram $__XILINX_RAM128X1D
init 1
abits 7
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__XILINX_RAM64X1D
or_next_if_better
endmatch
match $__XILINX_RAM128X1D
endmatch