add specific package imports and tests

frontends/ast/simplify.cc

@@ -1123,16 +1123,39 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 				}
 
 				if (package_node) {
-					// Import all names from the package into current scope
+					bool is_wildcard = child->children.empty();
+					std::set<std::string> import_items;
+					
+					// For specific imports, collect the list of items to import
+					if (!is_wildcard) {
+						for (auto& import_item : child->children) {
+							import_items.insert(import_item->str);
+						}
+					}
+					
+					// Import names from the package into current scope
 					for (auto& pkg_child : package_node->children) {
+						// Check if this is a specific import and if this item should be imported
+						if (!is_wildcard && import_items.count(pkg_child->str) == 0)
+							continue;
+						
 						if (pkg_child->type == AST_PARAMETER || pkg_child->type == AST_LOCALPARAM ||
 							pkg_child->type == AST_TYPEDEF || pkg_child->type == AST_FUNCTION ||
 							pkg_child->type == AST_TASK || pkg_child->type == AST_ENUM) {
+							// For wildcard imports, check if item already exists (from specific import)
+							if (is_wildcard && current_scope.count(pkg_child->str) > 0)
+								continue;
 							current_scope[pkg_child->str] = pkg_child.get();
 						}
 						if (pkg_child->type == AST_ENUM) {
 							for (auto& enode : pkg_child->children) {
 								log_assert(enode->type==AST_ENUM_ITEM);
+								// Check if this enum item should be imported
+								if (!is_wildcard && import_items.count(enode->str) == 0)
+									continue;
+								// For wildcard imports, check if item already exists (from specific import)
+								if (is_wildcard && current_scope.count(enode->str) > 0)
+									continue;
 								if (current_scope.count(enode->str) == 0)
 									current_scope[enode->str] = enode.get();
 								else

frontends/verilog/verilog_parser.y

@@ -428,6 +428,7 @@
 	#include <map>
 	#include <string>
 	#include <memory>
+	#include <vector>
 	#include "frontends/verilog/verilog_frontend.h"
 
 	struct specify_target {
@@ -462,6 +463,7 @@
 
 	using string_t = std::unique_ptr<std::string>;
 	using ast_t = std::unique_ptr<YOSYS_NAMESPACE_PREFIX AST::AstNode>;
+	using ast_list_t = std::vector<ast_t>;
 	using al_t = std::unique_ptr<YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, std::unique_ptr<YOSYS_NAMESPACE_PREFIX AST::AstNode>>>;
 	using specify_target_ptr_t = std::unique_ptr<struct specify_target>;
 	using specify_triple_ptr_t = std::unique_ptr<struct specify_triple>;
@@ -557,6 +559,8 @@
 %type <ast_t> struct_union
 %type <ast_node_type_t> asgn_binop inc_or_dec_op
 %type <ast_t> genvar_identifier
+%type <ast_list_t> import_item_list
+%type <ast_t> import_item
 
 %type <specify_target_ptr_t> specify_target
 %type <specify_triple_ptr_t> specify_triple specify_opt_triple
@@ -830,10 +834,37 @@ package_body_stmt:
 
 import_stmt:
 	TOK_IMPORT hierarchical_id TOK_PACKAGESEP TOK_ASTER TOK_SEMICOL {
-		// Create an import node to track package imports
+		// Create an import node to track specific and wildcard package imports
 		auto import_node = std::make_unique<AstNode>(@$, AST_IMPORT);
 		import_node->str = *$2;
 		extra->ast_stack.back()->children.push_back(std::move(import_node));
+	} |
+	TOK_IMPORT hierarchical_id TOK_PACKAGESEP import_item_list TOK_SEMICOL {
+		// Create an import node to track specific package imports
+		auto import_node = std::make_unique<AstNode>(@$, AST_IMPORT);
+		import_node->str = *$2;
+		// Move children from import_item_list to import_node
+		import_node->children = std::move($4);
+		extra->ast_stack.back()->children.push_back(std::move(import_node));
+	};
+
+import_item_list:
+	import_item {
+		ast_list_t list;
+		list.push_back(std::move($1));
+		$$ = std::move(list);
+	} |
+	import_item_list TOK_COMMA import_item {
+		$1.push_back(std::move($3));
+		$$ = std::move($1);
+	};
+
+import_item:
+	TOK_ID {
+		// Create a simple node to store the imported item name
+		auto item_node = std::make_unique<AstNode>(@$, AST_NONE);
+		item_node->str = *$1;
+		$$ = std::move(item_node);
 	};
 
 interface:

tests/verilog/package_import_specific.sv

@@ -0,0 +1,14 @@
+package package_import_specific;
+
+  localparam integer
+    DATA_WIDTH = 8,
+    ADDR_WIDTH = 4;
+
+  localparam logic [2:0]
+    IDLE  = 3'b000,
+    START = 3'b001,
+    DATA  = 3'b010,
+    STOP  = 3'b100,
+    DONE  = 3'b101;
+
+endpackage

tests/verilog/package_import_specific.ys

@@ -0,0 +1,5 @@
+read_verilog -sv package_import_specific.sv
+read_verilog -sv package_import_specific_module.sv
+hierarchy -check
+proc
+opt -full

tests/verilog/package_import_specific_module.sv

@@ -0,0 +1,16 @@
+import package_import_specific::DATA_WIDTH;
+import package_import_specific::IDLE;
+
+module package_import_specific_module;
+  logic [DATA_WIDTH-1:0] data;
+  logic [3:0] addr;
+  logic [2:0] state;
+
+  always_comb begin
+    case (state)
+      IDLE: data = 8'h00;
+      default: data = 8'hFF;
+    endcase
+  end
+
+endmodule