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add specific package imports and tests

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Rahul Bhagwat 2025-11-08 23:05:10 +05:30
parent 5d0847f6fb
commit 224109151d
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5 changed files with 91 additions and 2 deletions
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tests/verilog/package_import_specific_module.sv Normal file
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import package_import_specific::DATA_WIDTH;
import package_import_specific::IDLE;
module package_import_specific_module;
logic [DATA_WIDTH-1:0] data;
logic [3:0] addr;
logic [2:0] state;
always_comb begin
case (state)
IDLE: data = 8'h00;
default: data = 8'hFF;
endcase
end
endmodule