mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Same for variable length

Browse source
This commit is contained in:
Eddie Hung 2019-08-23 16:13:16 -07:00
parent b1caf7be5e
commit 2217d926a9
1 changed files with 10 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
passes/pmgen/xilinx_srl.pmg
View file

@ -181,7 +181,7 @@ endcode
pattern variable pattern variable
state <IdString> clk_port state <IdString> clk_port en_port
state <int> shiftx_width state <int> shiftx_width
state <int> slice state <int> slice
udata <int> minlen udata <int> minlen
@ -207,12 +207,18 @@ match first
set slice idx set slice idx
endmatch endmatch
code clk_port code clk_port en_port
if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
clk_port = \C; clk_port = \C;
else if (first->type.in($dff, $dffe)) else if (first->type.in($dff, $dffe))
clk_port = \CLK; clk_port = \CLK;
else log_abort(); else log_abort();
if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
en_port = \E;
else if (first->type.in($dff, $dffe))
en_port = \EN;
else log_abort();
chain.emplace_back(first, slice); chain.emplace_back(first, slice);
subpattern(tail); subpattern(tail);
finally finally
@ -229,6 +235,7 @@ arg shiftx
arg shiftx_width arg shiftx_width
arg slice arg slice
arg clk_port arg clk_port
arg en_port
match next match next
semioptional semioptional
@ -241,6 +248,7 @@ match next
index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
filter port(next, clk_port) == port(first, clk_port) filter port(next, clk_port) == port(first, clk_port)
filter en_port == IdString() || port(next, en_port) == port(first, en_port)
set slice idx set slice idx
endmatch endmatch