mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-21 05:13:40 +00:00
Code Activity

Added "dump" command (part ilang backend)

Browse source
This commit is contained in:
Clifford Wolf 2013-06-02 17:53:30 +02:00
parent 5f2c5f9017
commit 21d9251e52
4 changed files with 119 additions and 29 deletions
Download patch file Download diff file Expand all files Collapse all files

14
kernel/rtlil.cc
View file

@ -101,7 +101,7 @@ std::string RTLIL::Const::as_string() const
return ret;
}
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name)
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)
return true;
@ -112,7 +112,7 @@ bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name)
return false;
}
bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name)
bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
{
if (full_selection)
return true;
@ -121,14 +121,14 @@ bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name)
return false;
}
bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name)
bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
{
if (full_selection)
return true;
if (selected_modules.count(mod_name) > 0)
return true;
if (selected_members.count(mod_name) > 0)
if (selected_members[mod_name].count(memb_name) > 0)
if (selected_members.at(mod_name).count(memb_name) > 0)
return true;
return false;
}
@ -217,7 +217,7 @@ void RTLIL::Design::optimize()
it.second.optimize(this);
}
bool RTLIL::Design::selected_module(RTLIL::IdString mod_name)
bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
@ -226,7 +226,7 @@ bool RTLIL::Design::selected_module(RTLIL::IdString mod_name)
return selection_stack.back().selected_module(mod_name);
}
bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name)
bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;
@ -235,7 +235,7 @@ bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name)
return selection_stack.back().selected_whole_module(mod_name);
}
bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name)
bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
{
if (!selected_active_module.empty() && mod_name != selected_active_module)
return false;