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test dlatchsr and adlatch

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This commit is contained in:
Miodrag Milanovic 2022-02-16 13:58:51 +01:00
parent 271ac28b41
commit 21baf48e04
4 changed files with 94 additions and 4 deletions
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tests/sim/sim_dlatchsr.ys Normal file
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read_verilog -icells <<EOT
module dlatchsr(input d, set, clr, en, output reg q);
$dlatchsr #(.EN_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(1)) uut (.EN(en), .SET(set), .CLR(clr), .D(d), .Q(q));
endmodule
EOT
proc
opt_dff
stat
select -assert-count 1 t:$dlatchsr
sim -r tb_dlatchsr.fst -scope tb_dlatchsr.uut -sim-cmp dlatchsr