3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-18 08:18:56 +00:00

Add tests

This commit is contained in:
Gus Smith 2026-01-06 10:38:03 -08:00
parent 5b7d436851
commit 21709e7f33
2 changed files with 18 additions and 0 deletions

View file

@ -0,0 +1,10 @@
module json_param_defaults #(
parameter WIDTH = 8,
parameter SIGNED = 1
) (
input [WIDTH-1:0] a,
output [WIDTH-1:0] y
);
wire [WIDTH-1:0] y_int = a << SIGNED;
assign y = y_int;
endmodule

View file

@ -0,0 +1,8 @@
! mkdir -p temp
read_verilog -sv json_param_defaults.v
write_json temp/json_param_defaults.json
design -reset
read_json temp/json_param_defaults.json
write_verilog -noattr temp/json_param_defaults.v
! grep -qF "parameter WIDTH = 32'd8" temp/json_param_defaults.v
! grep -qF "parameter SIGNED = 32'd1" temp/json_param_defaults.v