From 21686f0d9d8bf13a6873b923b6751c83b98281bb Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 23 Jun 2023 19:40:29 +0200 Subject: [PATCH] verific: import src attribute on $memrd/$memwr cells --- frontends/verific/verific.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 989e2173b..0dd785ec3 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1649,6 +1649,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma cell->parameters[ID::TRANSPARENT] = false; cell->parameters[ID::ABITS] = GetSize(addr); cell->parameters[ID::WIDTH] = GetSize(data); + import_attributes(cell->attributes, inst); cell->setPort(ID::CLK, RTLIL::State::Sx); cell->setPort(ID::EN, RTLIL::State::Sx); cell->setPort(ID::ADDR, addr); @@ -1678,6 +1679,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma cell->parameters[ID::PRIORITY] = 0; cell->parameters[ID::ABITS] = GetSize(addr); cell->parameters[ID::WIDTH] = GetSize(data); + import_attributes(cell->attributes, inst); cell->setPort(ID::EN, RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data))); cell->setPort(ID::CLK, RTLIL::State::S0); cell->setPort(ID::ADDR, addr);