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Add rtlil string getters

This commit is contained in:
nella 2026-01-14 15:37:18 +01:00
parent b332279baf
commit 210b733555
3 changed files with 113 additions and 0 deletions

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@ -31,6 +31,7 @@
#include <charconv>
#include <optional>
#include <string_view>
#include <sstream>
YOSYS_NAMESPACE_BEGIN
@ -1548,6 +1549,13 @@ void RTLIL::Design::pop_selection()
push_full_selection();
}
std::string RTLIL::Design::to_rtlil_str(bool only_selected) const
{
std::ostringstream f;
RTLIL_BACKEND::dump_design(f, const_cast<RTLIL::Design*>(this), only_selected);
return f.str();
}
std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
{
bool include_partials = partials == RTLIL::SELECT_ALL;
@ -4288,6 +4296,13 @@ RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpe
return sig;
}
std::string RTLIL::Module::to_rtlil_str() const
{
std::ostringstream f;
RTLIL_BACKEND::dump_module(f, "", const_cast<RTLIL::Module*>(this), design, false);
return f.str();
}
RTLIL::Wire::Wire()
{
static unsigned int hashidx_count = 123456789;
@ -4315,6 +4330,13 @@ RTLIL::Wire::~Wire()
#endif
}
std::string RTLIL::Wire::to_rtlil_str() const
{
std::ostringstream f;
RTLIL_BACKEND::dump_wire(f, "", this);
return f.str();
}
#ifdef YOSYS_ENABLE_PYTHON
static std::map<unsigned int, RTLIL::Wire*> all_wires;
std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
@ -4337,6 +4359,13 @@ RTLIL::Memory::Memory()
#endif
}
std::string RTLIL::Memory::to_rtlil_str() const
{
std::ostringstream f;
RTLIL_BACKEND::dump_memory(f, "", this);
return f.str();
}
RTLIL::Process::Process() : module(nullptr)
{
static unsigned int hashidx_count = 123456789;
@ -4344,6 +4373,13 @@ RTLIL::Process::Process() : module(nullptr)
hashidx_ = hashidx_count;
}
std::string RTLIL::Process::to_rtlil_str() const
{
std::ostringstream f;
RTLIL_BACKEND::dump_proc(f, "", this);
return f.str();
}
RTLIL::Cell::Cell() : module(nullptr)
{
static unsigned int hashidx_count = 123456789;
@ -4365,6 +4401,13 @@ RTLIL::Cell::~Cell()
#endif
}
std::string RTLIL::Cell::to_rtlil_str() const
{
std::ostringstream f;
RTLIL_BACKEND::dump_cell(f, "", this);
return f.str();
}
#ifdef YOSYS_ENABLE_PYTHON
static std::map<unsigned int, RTLIL::Cell*> all_cells;
std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)