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Add rtlil string getters
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3 changed files with 113 additions and 0 deletions
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@ -31,6 +31,7 @@
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#include <charconv>
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#include <optional>
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#include <string_view>
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#include <sstream>
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YOSYS_NAMESPACE_BEGIN
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@ -1548,6 +1549,13 @@ void RTLIL::Design::pop_selection()
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push_full_selection();
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}
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std::string RTLIL::Design::to_rtlil_str(bool only_selected) const
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{
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std::ostringstream f;
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RTLIL_BACKEND::dump_design(f, const_cast<RTLIL::Design*>(this), only_selected);
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return f.str();
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}
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std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
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{
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bool include_partials = partials == RTLIL::SELECT_ALL;
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@ -4288,6 +4296,13 @@ RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpe
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return sig;
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}
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std::string RTLIL::Module::to_rtlil_str() const
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{
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std::ostringstream f;
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RTLIL_BACKEND::dump_module(f, "", const_cast<RTLIL::Module*>(this), design, false);
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return f.str();
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}
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RTLIL::Wire::Wire()
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{
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static unsigned int hashidx_count = 123456789;
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@ -4315,6 +4330,13 @@ RTLIL::Wire::~Wire()
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#endif
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}
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std::string RTLIL::Wire::to_rtlil_str() const
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{
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std::ostringstream f;
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RTLIL_BACKEND::dump_wire(f, "", this);
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return f.str();
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}
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#ifdef YOSYS_ENABLE_PYTHON
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static std::map<unsigned int, RTLIL::Wire*> all_wires;
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std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
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@ -4337,6 +4359,13 @@ RTLIL::Memory::Memory()
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#endif
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}
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std::string RTLIL::Memory::to_rtlil_str() const
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{
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std::ostringstream f;
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RTLIL_BACKEND::dump_memory(f, "", this);
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return f.str();
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}
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RTLIL::Process::Process() : module(nullptr)
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{
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static unsigned int hashidx_count = 123456789;
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@ -4344,6 +4373,13 @@ RTLIL::Process::Process() : module(nullptr)
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hashidx_ = hashidx_count;
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}
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std::string RTLIL::Process::to_rtlil_str() const
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{
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std::ostringstream f;
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RTLIL_BACKEND::dump_proc(f, "", this);
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return f.str();
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}
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RTLIL::Cell::Cell() : module(nullptr)
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{
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static unsigned int hashidx_count = 123456789;
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@ -4365,6 +4401,13 @@ RTLIL::Cell::~Cell()
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#endif
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}
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std::string RTLIL::Cell::to_rtlil_str() const
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{
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std::ostringstream f;
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RTLIL_BACKEND::dump_cell(f, "", this);
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return f.str();
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}
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#ifdef YOSYS_ENABLE_PYTHON
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static std::map<unsigned int, RTLIL::Cell*> all_cells;
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std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
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