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Remove check for cell->name[0] == '$'

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This commit is contained in:
Eddie Hung 2019-02-06 14:53:40 -08:00
parent c373640a3a
commit 20ca795b87
1 changed files with 1 additions and 1 deletions
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2
backends/verilog/verilog_backend.cc
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@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
std::string init; std::string init;
if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
std::stringstream ss; std::stringstream ss;
dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
init = ss.str(); init = ss.str();