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Merge branch 'YosysHQ:main' into main

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This commit is contained in:
Akash Levy 2025-02-04 10:27:16 -08:00 • committed by GitHub
commit 20c358bce2
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2 changed files with 19 additions and 9 deletions
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2
Makefile
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@ -171,7 +171,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
YOSYS_VER := 0.49+10
YOSYS_VER := 0.49+17
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo

26
passes/techmap/alumacc.cc
View file

@ -406,11 +406,6 @@ struct AlumaccWorker
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
if (B < A && GetSize(B)) {
cmp_less = !cmp_less;
std::swap(A, B);
}
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
@ -419,6 +414,16 @@ struct AlumaccWorker
break;
}
if (n == nullptr) {
for (auto node : sig_alu[RTLIL::SigSig(B, A)])
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node;
cmp_less = !cmp_less;
std::swap(A, B);
break;
}
}
if (n == nullptr) {
n = new alunode_t;
n->a = A;
@ -446,9 +451,6 @@ struct AlumaccWorker
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
if (B < A && GetSize(B))
std::swap(A, B);
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
@ -457,6 +459,14 @@ struct AlumaccWorker
break;
}
if (n == nullptr) {
for (auto node : sig_alu[RTLIL::SigSig(B, A)])
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node;
break;
}
}
if (n != nullptr) {
log(" creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
n->cells.push_back(cell);