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403
manual/PRESENTATION_Intro.tex
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@ -8,247 +8,6 @@
\iffalse
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Representations of (digital) Circuits}
\begin{frame}[t]{\subsecname}
\begin{itemize}
\item Graphical
\begin{itemize}
\item \alert<1>{Schematic Diagram}
\item \alert<2>{Physical Layout}
\end{itemize}
\bigskip
\item Non-graphical
\begin{itemize}
\item \alert<3>{Netlists}
\item \alert<4>{Hardware Description Languages (HDLs)}
\end{itemize}
\end{itemize}
\bigskip
\begin{block}{Definition:
\only<1>{Schematic Diagram}%
\only<2>{Physical Layout}%
\only<3>{Netlists}%
\only<4>{Hardware Description Languages (HDLs)}}
\only<1>{
Graphical representation of the circuit topology. Circuit elements
are represented by symbols and electrical connections by lines. The geometric
layout is for readability only.
}%
\only<2>{
The actual physical geometry of the device (PCB or ASIC manufacturing masks).
This is the final product of the design process.
}%
\only<3>{
A list of circuit elements and a list of connections. This is the raw circuit
topology.
}%
\only<4>{
Computer languages (like programming languages) that can be used to describe
circuits. HDLs are much more powerful in describing huge circuits than
schematic diagrams.
}%
\end{block}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\fi
\subsection{Levels of Abstraction for Digital Circuits}
\begin{frame}[t]{\subsecname}
\begin{itemize}
\item \alert<1>{System Level}
\item \alert<2>{High Level}
\item \alert<3>{Behavioral Level}
\item \alert<4>{Register-Transfer Level (RTL)}
\item \alert<5>{Logical Gate Level}
\item \alert<6>{Physical Gate Level}
\item \alert<7>{Switch Level}
\end{itemize}
\bigskip
\begin{block}{Definition:
\only<1>{System Level}%
\only<2>{High Level}%
\only<3>{Behavioral Level}%
\only<4>{Register-Transfer Level (RTL)}%
\only<5>{Logical Gate Level}%
\only<6>{Physical Gate Level}%
\only<7>{Switch Level}}
\only<1>{
Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
}%
\only<2>{
Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
}%
\only<3>{
Cycle-accurate description of circuit in hardware description language (Verilog, VHDL, etc.).
}%
\only<4>{
List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc.
}%
\only<5>{
Netlist of single-bit registers and basic logic gates (such as AND, OR,
NOT, etc.). Popular form: And-Inverter-Graphs (AIGs) with pairs of primary
inputs and outputs for each register bit.
}%
\only<6>{
Netlist of cells that actually are available on the target architecture
(such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for
area, power, and/or speed (static timing or number of logic levels).
}%
\only<7>{
Netlist of individual transistors.
}%
\end{block}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Digital Circuit Synthesis}
\begin{frame}{\subsecname}
Synthesis Tools (such as Yosys) can transform HDL code to circuits:
\bigskip
\begin{center}
\begin{tikzpicture}[scale=0.8, every node/.style={transform shape}]
\tikzstyle{lvl} = [draw, fill=MyBlue, rectangle, minimum height=2em, minimum width=15em]
\node[lvl] (sys) {System Level};
\node[lvl] (hl) [below of=sys] {High Level};
\node[lvl] (beh) [below of=hl] {Behavioral Level};
\node[lvl] (rtl) [below of=beh] {Register-Transfer Level (RTL)};
\node[lvl] (lg) [below of=rtl] {Logical Gate Level};
\node[lvl] (pg) [below of=lg] {Physical Gate Level};
\node[lvl] (sw) [below of=pg] {Switch Level};
\draw[dotted] (sys.east) -- ++(1,0) coordinate (sysx);
\draw[dotted] (hl.east) -- ++(1,0) coordinate (hlx);
\draw[dotted] (beh.east) -- ++(1,0) coordinate (behx);
\draw[dotted] (rtl.east) -- ++(1,0) coordinate (rtlx);
\draw[dotted] (lg.east) -- ++(1,0) coordinate (lgx);
\draw[dotted] (pg.east) -- ++(1,0) coordinate (pgx);
\draw[dotted] (sw.east) -- ++(1,0) coordinate (swx);
\draw[gray,|->] (sysx) -- node[right] {System Design} (hlx);
\draw[|->|] (hlx) -- node[right] {High Level Synthesis (HLS)} (behx);
\draw[->|] (behx) -- node[right] {Behavioral Synthesis} (rtlx);
\draw[->|] (rtlx) -- node[right] {RTL Synthesis} (lgx);
\draw[->|] (lgx) -- node[right] {Logic Synthesis} (pgx);
\draw[gray,->|] (pgx) -- node[right] {Cell Library} (swx);
\draw[dotted] (behx) -- ++(4,0) coordinate (a);
\draw[dotted] (pgx) -- ++(4,0) coordinate (b);
\draw[|->|] (a) -- node[right] {Yosys} (b);
\end{tikzpicture}
\end{center}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{What Yosys can and can't do}
\begin{frame}{\subsecname}
Things Yosys can do:
\begin{itemize}
\item Read and process (most of) modern Verilog-2005 code.
\item Perform all kinds of operations on netlist (RTL, Logic, Gate).
\item Perform logic optimizations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
\end{itemize}
\bigskip
Things Yosys can't do:
\begin{itemize}
\item Process high-level languages such as C/C++/SystemC.
\item Create physical layouts (place\&route).
\end{itemize}
\bigskip
A typical flow combines Yosys with with a low-level implementation tool, such
as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC designs.
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Yosys Data- and Control-Flow}
\begin{frame}{\subsecname}
A (usually short) synthesis script controls Yosys.
This scripts contain three types of commands:
\begin{itemize}
\item {\bf Frontends}, that read input files (usually Verilog).
\item {\bf Passes}, that perform transformations on the design in memory.
\item {\bf Backends}, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, \dots).
\end{itemize}
\bigskip
\begin{center}
\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
\path (-1.5,3) coordinate (cursor);
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Frontend} ++(1,3) coordinate (cursor);
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
\draw[fill=green!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Pass} ++(1,3) coordinate (cursor);
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
\draw[fill=orange!10] ($ (cursor) + (1,-3) $) rectangle node[rotate=90] {Backend} ++(1,3) coordinate (cursor);
\draw[-latex] ($ (cursor) + (0,-1.5) $) -- ++(1,0);
\path (-3,-0.5) coordinate (cursor);
\draw (cursor) -- node[below] {HDL} ++(3,0) coordinate (cursor);
\draw[|-|] (cursor) -- node[below] {Internal Format (RTLIL)} ++(8,0) coordinate (cursor);
\draw (cursor) -- node[below] {Netlist} ++(3,0);
\path (-3,3.5) coordinate (cursor);
\draw[-] (cursor) -- node[above] {High-Level} ++(3,0) coordinate (cursor);
\draw[-] (cursor) -- ++(8,0) coordinate (cursor);
\draw[->] (cursor) -- node[above] {Low-Level} ++(3,0);
\end{tikzpicture}
\end{center}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Program Components and Data Formats}
\begin{frame}{\subsecname}
\begin{center}
\begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
\tikzstyle{process} = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
\tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
\node[process] (vlog) {Verilog Frontend};
\node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
\node[process] (ilang) [right of=vhdl] {Other Frontends};
\node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST};
\node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend};
\node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL};
\node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes};
\node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend};
\node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend};
\node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends};
\draw[-latex] (vlog) -- (ast);
\draw[-latex] (vhdl) -- (ast);
\draw[-latex] (ast) -- (astfe);
\draw[-latex] (astfe) -- (rtlil);
\draw[-latex] (ilang) -- (rtlil);
\draw[latex-latex] (rtlil) -- (pass);
\draw[-latex] (rtlil) -- (vlbe);
\draw[-latex] (rtlil) -- (ilangbe);
\draw[-latex] (rtlil) -- (otherbe);
\end{tikzpicture}
\end{center}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Example Project}
\begin{frame}[t]{\subsecname}
@ -265,168 +24,6 @@ Direct link to the files: \\ \footnotesize
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}[t]{\subsecname{} -- Synthesis Script}
\setbeamercolor{alerted text}{fg=white,bg=red}
\begin{minipage}[t]{6cm}
\tt\scriptsize
{\color{YosysGreen}\# read design}\\
\boxalert<1>{read\_verilog counter.v}\\
\boxalert<2>{hierarchy -check -top counter}
\medskip
{\color{YosysGreen}\# the high-level stuff}\\
\boxalert<3>{proc}; \boxalert<4>{opt}; \boxalert<5>{fsm}; \boxalert<6>{opt}; \boxalert<7>{memory}; \boxalert<8>{opt}
\medskip
{\color{YosysGreen}\# mapping to internal cell library}\\
\boxalert<9>{techmap}; \boxalert<10>{opt}
\end{minipage}
\begin{minipage}[t]{5cm}
\tt\scriptsize
{\color{YosysGreen}\# mapping flip-flops to mycells.lib}\\
\boxalert<11>{dfflibmap -liberty mycells.lib}
\medskip
{\color{YosysGreen}\# mapping logic to mycells.lib}\\
\boxalert<12>{abc -liberty mycells.lib}
\medskip
{\color{YosysGreen}\# cleanup}\\
\boxalert<13>{clean}
\medskip
{\color{YosysGreen}\# write synthesized design}\\
\boxalert<14>{write\_verilog synth.v}
\end{minipage}
\vskip1cm
\begin{block}{Command: \tt
\only<1>{read\_verilog counter.v}%
\only<2>{hierarchy -check -top counter}%
\only<3>{proc}%
\only<4>{opt}%
\only<5>{fsm}%
\only<6>{opt}%
\only<7>{memory}%
\only<8>{opt}%
\only<9>{techmap}%
\only<10>{opt}%
\only<11>{dfflibmap -liberty mycells.lib}%
\only<12>{abc -liberty mycells.lib}%
\only<13>{clean}%
\only<14>{write\_verilog synth.v}}
\only<1>{
Read Verilog source file and convert to internal representation.
}%
\only<2>{
Elaborate the design hierarchy. Should always be the first
command after reading the design. Can re-run AST front-end.
}%
\only<3>{
Convert ``processes'' (the internal representation of behavioral
Verilog code) into multiplexers and registers.
}%
\only<4>{
Perform some basic optimizations and cleanups.
}%
\only<5>{
Analyze and optimize finite state machines.
}%
\only<6>{
Perform some basic optimizations and cleanups.
}%
\only<7>{
Analyze memories and create circuits to implement them.
}%
\only<8>{
Perform some basic optimizations and cleanups.
}%
\only<9>{
Map coarse-grain RTL cells (adders, etc.) to fine-grain
logic gates (AND, OR, NOT, etc.).
}%
\only<10>{
Perform some basic optimizations and cleanups.
}%
\only<11>{
Map registers to available hardware flip-flops.
}%
\only<12>{
Map logic to available hardware gates.
}%
\only<13>{
Clean up the design (just the last step of {\tt opt}).
}%
\only<14>{
Write final synthesis result to output file.
}%
\end{block}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
\end{frame}
\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
\end{columns}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Running the Synthesis Script}
\begin{frame}[t, fragile]{\subsecname{} -- Step 1/4}
\begin{verbatim}
read_verilog counter.v
hierarchy -check -top counter
\end{verbatim}
\vfill
\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_00.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Step 2/4}
\begin{verbatim}
proc; opt; fsm; opt; memory; opt
\end{verbatim}
\vfill
\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_01.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Step 3/4}
\begin{verbatim}
techmap; opt
\end{verbatim}
\vfill
\includegraphics[width=\linewidth,trim=0 0cm 0 2cm]{PRESENTATION_Intro/counter_02.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Step 4/4}
\begin{verbatim}
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib
clean
\end{verbatim}
\vfill\hfil
\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{The synth command}
\begin{frame}[fragile]{\subsecname{}}

4
manual/PRESENTATION_Intro/.gitignore vendored
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@ -1,4 +0,0 @@
counter_00.dot
counter_01.dot
counter_02.dot
counter_03.dot

10
manual/PRESENTATION_Intro/Makefile
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@ -1,10 +0,0 @@
all: counter_00.pdf counter_01.pdf counter_02.pdf counter_03.pdf
counter_00.pdf: counter.v counter.ys mycells.lib
../../yosys counter.ys
counter_01.pdf: counter_00.pdf
counter_02.pdf: counter_00.pdf
counter_03.pdf: counter_00.pdf

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manual/PRESENTATION_Intro/counter.v
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@ -1,12 +0,0 @@
module counter (clk, rst, en, count);
input clk, rst, en;
output reg [1:0] count;
always @(posedge clk)
if (rst)
count <= 2'd0;
else if (en)
count <= count + 2'd1;
endmodule

27
manual/PRESENTATION_Intro/counter.ys
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@ -1,27 +0,0 @@
# read design
read_verilog counter.v
hierarchy -check -top counter
show -notitle -stretch -format pdf -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
show -notitle -stretch -format pdf -prefix counter_01
# mapping to internal cell library
techmap; opt
splitnets -ports;;
show -notitle -stretch -format pdf -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03

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manual/PRESENTATION_Intro/mycells.lib
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@ -1,38 +0,0 @@
library(demo) {
cell(BUF) {
area: 6;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A"; }
}
cell(NOT) {
area: 3;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A'"; }
}
cell(NAND) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A*B)'"; }
}
cell(NOR) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A+B)'"; }
}
cell(DFF) {
area: 18;
ff(IQ, IQN) { clocked_on: C;
next_state: D; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
}
}

23
manual/PRESENTATION_Intro/mycells.v
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@ -1,23 +0,0 @@
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
module DFF(C, D, Q);
input C, D;
output reg Q;
always @(posedge C)
Q <= D;
endmodule