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Move presentation intro example

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Rework images makefile a bit to get it to import and build from resources folder(s).
Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
This commit is contained in:
Krystine Sherwin 2023-08-03 09:20:29 +12:00
parent cd6e63e1a9
commit 20c2708383
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15 changed files with 249 additions and 438 deletions
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27
docs/resources/PRESENTATION_Intro/counter_outputs.ys Normal file
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# read design
read_verilog counter.v
hierarchy -check -top counter
show -notitle -format dot -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
show -notitle -format dot -prefix counter_01
# mapping to internal cell library
techmap; opt
splitnets -ports;;
show -notitle -format dot -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
show -notitle -lib mycells.v -format dot -prefix counter_03