Move presentation intro example

Rework images makefile a bit to get it to import and build from resources folder(s).
Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.

docs/resources/PRESENTATION_Intro/counter.ys

@@ -0,0 +1,21 @@
+# read design
+read_verilog counter.v
+hierarchy -check -top counter
+
+# the high-level stuff
+proc; opt; memory; opt; fsm; opt
+
+# mapping to internal cell library
+techmap; opt
+
+# mapping flip-flops to mycells.lib
+dfflibmap -liberty mycells.lib
+
+# mapping logic to mycells.lib
+abc -liberty mycells.lib
+
+# cleanup
+clean
+
+# write synthesized design
+write_verilog synth.v