3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-12 06:00:55 +00:00

verilog_location: rename location to Location to avoid conflict with Pass::location

This commit is contained in:
Emil J. Tywoniak 2025-08-08 16:22:54 +02:00
parent 65b53e6473
commit 20b2e47b42
8 changed files with 28 additions and 32 deletions

View file

@ -164,7 +164,7 @@ namespace AST
AST_BIND
};
using AstSrcLocType = location;
using AstSrcLocType = Location;
// convert an node type to a string (e.g. for debug output)
std::string type2str(AstNodeType type);

View file

@ -684,7 +684,7 @@ static bool contains_unbased_unsized(const AstNode *node)
// adds a wire to the current module with the given name that matches the
// dimensions of the given wire reference
void add_wire_for_ref(location loc, const RTLIL::Wire *ref, const std::string &str)
void add_wire_for_ref(Location loc, const RTLIL::Wire *ref, const std::string &str)
{
auto left = AstNode::mkconst_int(loc, ref->width - 1 + ref->start_offset, true);
auto right = AstNode::mkconst_int(loc, ref->start_offset, true);