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tests/bugpoint: More tests

More coverage.
This commit is contained in:
Krystine Sherwin 2025-05-16 16:55:54 +12:00
parent 2d8fa9fbef
commit 20b0ab26b1
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7 changed files with 248 additions and 5 deletions

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@ -1,3 +1,5 @@
*.il
bugpoint-case.*
*.log
*.err
*.temp
run-test.mk

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write_file fail.temp << EOF
logger -expect error "Missing -script or -command option." 1
bugpoint -suffix fail -yosys ../../yosys
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "do not crash on this design" 1
bugpoint -suffix fail -yosys ../../yosys -command "dump"
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "returned value 3 instead of expected 7" 1
bugpoint -suffix fail -yosys ../../yosys -command raise_error -expect-return 7
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "not found in the log file!" 1
bugpoint -suffix fail -yosys ../../yosys -command raise_error -grep "nope"
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "not found in stderr log!" 1
bugpoint -suffix fail -yosys ../../yosys -command raise_error -err-grep "nope"
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp

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read_rtlil mods.il
select -assert-count 7 w:*
select -assert-mod-count 3 =*
select -assert-count 4 c:*
design -stash base
# everything is removed by default
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
# don't remove wires
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -modules -cells
select -assert-count 3 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
# don't remove cells or their connections
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules
select -assert-count 5 w:*
select -assert-mod-count 1 =*
select -assert-count 4 c:*
# don't remove cells but do remove their connections
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules -connections
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-count 4 c:*
# don't remove modules
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -cells
select -assert-count 1 w:*
select -assert-mod-count 3 =*
select -assert-none c:*
# can keep wires
design -load base
setattr -set bugpoint_keep 1 w:w_b
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
select -assert-count 2 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
# a wire with keep won't keep the cell/module containing it
design -load base
setattr -set bugpoint_keep 1 w:w_o
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
# can keep cells (and do it without the associated module)
design -load base
setattr -set bugpoint_keep 1 c:c_a
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-count 1 c:*
# can keep modules
design -load base
setattr -mod -set bugpoint_keep 1 m_a
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 2 =*
select -assert-none c:*
# minimize to just the path connecting w_a and w_c
# which happens via w_b, w_i, w_o, m_a, c_a and c_b
write_file script.temp << EOF
select -assert-none w:w_a %co* w:w_c %ci* %i
EOF
design -load base
bugpoint -suffix mods -yosys ../../yosys -script script.temp -grep "Assertion failed"
select -assert-count 5 w:*
select -assert-mod-count 2 =*
select -assert-count 2 c:*

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tests/bugpoint/mods.il Normal file
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module \m_a
wire input 1 \w_i
wire output 2 \w_o
connect \w_o \w_i
end
module \m_b
wire input 1 \w_i
wire output 2 \w_o
end
attribute \top 1
module \top
attribute \raise_error 3
wire \w_a
wire \w_b
wire \w_c
cell \m_a \c_a
connect \w_i \w_a
connect \w_o \w_b
end
cell \m_a \c_b
connect \w_i \w_b
connect \w_o \w_c
end
cell \m_b \c_c
connect \w_i \w_c
connect \w_o \w_a
end
cell \m_b \c_d
connect \w_i 1'0
connect \w_o 1'1
end
end

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read_rtlil procs.il
select -assert-count 2 p:*
design -stash err_q
# processes get removed by default
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
select -assert-none p:*
# individual processes can be kept
design -load err_q
setattr -set bugpoint_keep 1 p:proc_a
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
select -assert-count 1 p:*
# all processes can be kept
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -wires
select -assert-count 2 p:*
# d and clock are connected after proc
design -load err_q
proc
select -assert-count 3 w:d %co
select -assert-count 3 w:clock %co
# no assigns means no d
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -assigns
proc
select -assert-count 1 w:d %co
# no updates means no clock
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -updates
proc
select -assert-count 1 w:clock %co
# can remove ports
design -load err_q
select -assert-count 5 x:*
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
select -assert-none x:*
# can keep ports
design -load err_q
setattr -set bugpoint_keep 1 i:d o:q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
select -assert-count 2 x:*

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tests/bugpoint/procs.il Normal file
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module \ff_with_en_and_sync_reset
wire $0\q[1:1]
wire $0\q[0:0]
attribute \raise_error 4
wire width 2 output 5 \q
wire width 2 input 4 \d
wire input 3 \enable
wire input 2 \reset
wire input 1 \clock
process \proc_a
assign $0\q[0:0] \q [0]
switch \reset
case 1'1
assign $0\q[0:0] 1'0
case
switch \enable
case 1'1
assign $0\q[0:0] \d [0]
case
end
end
sync posedge \clock
update \q [0] $0\q[0:0]
end
process \proc_b
assign $0\q[1:1] \q [1]
switch \reset
case 1'1
assign $0\q[1:1] 1'0
case
switch \enable
case 1'1
assign $0\q[1:1] \d [1]
case
end
end
sync posedge \clock
update \q [1] $0\q[1:1]
end
end

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@ -16,14 +16,14 @@ design -stash read
# raise_error with int exits with status
design -load read
bugpoint -yosys ../../yosys -command raise_error -expect-return 7
bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7
select -assert-mod-count 1 =*
select -assert-mod-count 1 top
# raise_error with string prints message and exits with 1
design -load read
rename top abc
bugpoint -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1
bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1
select -assert-mod-count 1 =*
select -assert-mod-count 1 other
@ -31,13 +31,13 @@ select -assert-mod-count 1 other
design -load read
rename def zzy
delete other
bugpoint -yosys ../../yosys -command raise_error -expect-return 1
bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1
select -assert-mod-count 1 =*
select -assert-mod-count 1 zzy
# raise_error -stderr prints to stderr and exits with 1
design -load read
rename top abc
bugpoint -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1
bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1
select -assert-mod-count 1 =*
select -assert-mod-count 1 other