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verilog: improved support for recursive functions

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This commit is contained in:
Zachary Snow 2020-12-31 17:23:36 -07:00
parent 48d0aeb094
commit 2085d9a55d
4 changed files with 99 additions and 8 deletions
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6
tests/various/fib.ys Normal file
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@ -0,0 +1,6 @@
read_verilog fib.v
hierarchy
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert