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fixup verilog doubleslash test

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- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
This commit is contained in:
Zachary Snow 2021-12-30 00:06:23 -07:00 • committed by Zachary Snow
parent 8c509a5659
commit 207af4196b
2 changed files with 3 additions and 0 deletions
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2
tests/verilog/doubleslash.ys
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@ -17,3 +17,5 @@ proc
opt -full
write_verilog doubleslash.v
design -reset
read_verilog doubleslash.v