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Import more std:: stuff into Yosys namespace

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This commit is contained in:
Clifford Wolf 2015-10-25 19:30:49 +01:00
parent da923c198e
commit 207736b4ee
39 changed files with 168 additions and 161 deletions
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4
backends/smt2/smt2.cc
View file

@ -244,8 +244,8 @@ struct Smt2Worker
int width = GetSize(sig_y);
if (type == 's' || type == 'd' || type == 'b') {
width = std::max(width, GetSize(cell->getPort("\\A")));
width = std::max(width, GetSize(cell->getPort("\\B")));
width = max(width, GetSize(cell->getPort("\\A")));
width = max(width, GetSize(cell->getPort("\\B")));
}
if (cell->hasPort("\\A")) {

10
backends/smv/smv.cc
View file

@ -244,13 +244,13 @@ struct SmvWorker
int width_y = GetSize(cell->getPort("\\Y"));
int shift_b_width = GetSize(sig_b);
int width_ay = std::max(GetSize(sig_a), width_y);
int width_ay = max(GetSize(sig_a), width_y);
int width = width_ay;
for (int i = 1, j = 0;; i <<= 1, j++)
if (width_ay < i) {
width = i-1;
shift_b_width = std::min(shift_b_width, j);
shift_b_width = min(shift_b_width, j);
break;
}
@ -361,8 +361,8 @@ struct SmvWorker
if (cell->type.in("$div", "$mod"))
{
int width_y = GetSize(cell->getPort("\\Y"));
int width = std::max(width_y, GetSize(cell->getPort("\\A")));
width = std::max(width, GetSize(cell->getPort("\\B")));
int width = max(width_y, GetSize(cell->getPort("\\A")));
width = max(width, GetSize(cell->getPort("\\B")));
string expr_a, expr_b, op;
if (cell->type == "$div") op = "/";
@ -384,7 +384,7 @@ struct SmvWorker
if (cell->type.in("$eq", "$ne", "$eqx", "$nex", "$lt", "$le", "$ge", "$gt"))
{
int width = std::max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
int width = max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
string expr_a, expr_b, op;
if (cell->type == "$eq") op = "=";

40
frontends/ast/genrtlil.cc
View file

@ -547,14 +547,14 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
switch (type)
{
case AST_CONSTANT:
width_hint = std::max(width_hint, int(bits.size()));
width_hint = max(width_hint, int(bits.size()));
if (!is_signed)
sign_hint = false;
break;
case AST_REALVALUE:
*found_real = true;
width_hint = std::max(width_hint, 32);
width_hint = max(width_hint, 32);
break;
case AST_IDENTIFIER:
@ -617,7 +617,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
this_width = range->range_left - range->range_right + 1;
sign_hint = false;
}
width_hint = std::max(width_hint, this_width);
width_hint = max(width_hint, this_width);
if (!id_ast->is_signed)
sign_hint = false;
break;
@ -627,7 +627,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (children[0]->type != AST_CONSTANT)
log_error("Left operand of tobits expression is not constant at %s:%d!\n", filename.c_str(), linenum);
children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
width_hint = std::max(width_hint, children[0]->bitsAsConst().as_int());
width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
break;
case AST_TO_SIGNED:
@ -646,7 +646,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
this_width += sub_width_hint;
}
width_hint = std::max(width_hint, this_width);
width_hint = max(width_hint, this_width);
sign_hint = false;
break;
@ -655,7 +655,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (children[0]->type != AST_CONSTANT)
log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
width_hint = std::max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
sign_hint = false;
break;
@ -678,7 +678,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_REDUCE_XOR:
case AST_REDUCE_XNOR:
case AST_REDUCE_BOOL:
width_hint = std::max(width_hint, 1);
width_hint = max(width_hint, 1);
sign_hint = false;
break;
@ -698,7 +698,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_NEX:
case AST_GE:
case AST_GT:
width_hint = std::max(width_hint, 1);
width_hint = max(width_hint, 1);
sign_hint = false;
break;
@ -714,7 +714,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_LOGIC_AND:
case AST_LOGIC_OR:
case AST_LOGIC_NOT:
width_hint = std::max(width_hint, 1);
width_hint = max(width_hint, 1);
sign_hint = false;
break;
@ -729,7 +729,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (!id2ast->children[0]->range_valid)
log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
width_hint = std::max(width_hint, this_width);
width_hint = max(width_hint, this_width);
break;
// everything should have been handled above -> print error if not.
@ -1054,7 +1054,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
int width = std::max(left.size(), right.size());
int width = max(left.size(), right.size());
if (width_hint > 0)
width = width_hint;
is_signed = children[0]->is_signed && children[1]->is_signed;
@ -1068,7 +1068,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = uniop2rtlil(this, type_name, std::max(width_hint, 1), arg);
RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
return sig;
}
@ -1077,7 +1077,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, std::max(width_hint, 1), arg) : arg;
RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
return sig;
}
@ -1123,7 +1123,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (0) { case AST_GE: type_name = "$ge"; }
if (0) { case AST_GT: type_name = "$gt"; }
{
int width = std::max(width_hint, 1);
int width = max(width_hint, 1);
width_hint = -1, sign_hint = true;
children[0]->detectSignWidthWorker(width_hint, sign_hint);
children[1]->detectSignWidthWorker(width_hint, sign_hint);
@ -1145,7 +1145,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
#if 0
int width = std::max(left.size(), right.size());
int width = max(left.size(), right.size());
if (width > width_hint && width_hint > 0)
width = width_hint;
if (width < width_hint) {
@ -1154,10 +1154,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
width = width_hint;
if (type == AST_MUL)
width = std::min(left.size() + right.size(), width_hint);
width = min(left.size() + right.size(), width_hint);
}
#else
int width = std::max(std::max(left.size(), right.size()), width_hint);
int width = max(max(left.size(), right.size()), width_hint);
#endif
is_signed = children[0]->is_signed && children[1]->is_signed;
return binop2rtlil(this, type_name, width, left, right);
@ -1169,14 +1169,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
{
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL();
return binop2rtlil(this, type_name, std::max(width_hint, 1), left, right);
return binop2rtlil(this, type_name, max(width_hint, 1), left, right);
}
// generate cells for unary operations: $logic_not
case AST_LOGIC_NOT:
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
return uniop2rtlil(this, "$logic_not", std::max(width_hint, 1), arg);
return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
}
// generate multiplexer for ternary operator (aka ?:-operator)
@ -1192,7 +1192,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (cond.size() > 1)
cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
int width = std::max(val1.size(), val2.size());
int width = max(val1.size(), val2.size());
is_signed = children[1]->is_signed && children[2]->is_signed;
widthExtend(this, val1, width, is_signed);
widthExtend(this, val2, width, is_signed);

24
frontends/ast/simplify.cc
View file

@ -398,7 +398,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
did_something = true;
children[0]->detectSignWidth(backup_width_hint, backup_sign_hint);
children[1]->detectSignWidth(width_hint, sign_hint);
width_hint = std::max(width_hint, backup_width_hint);
width_hint = max(width_hint, backup_width_hint);
child_0_is_self_determined = true;
break;
@ -412,7 +412,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
did_something = true;
if (!children[1]->range_valid)
log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum);
width_hint = std::max(width_hint, children[1]->range_left - children[1]->range_right + 1);
width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1);
}
break;
@ -733,8 +733,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
for (auto range : children[1]->children) {
if (!range->range_valid)
log_error("Non-constant range on memory decl at %s:%d.\n", filename.c_str(), linenum);
multirange_dimensions.push_back(std::min(range->range_left, range->range_right));
multirange_dimensions.push_back(std::max(range->range_left, range->range_right) - std::min(range->range_left, range->range_right) + 1);
multirange_dimensions.push_back(min(range->range_left, range->range_right));
multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1);
total_size *= multirange_dimensions.back();
}
delete children[1];
@ -1169,7 +1169,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
log_error("Non-constant array range on cell array at %s:%d.\n", filename.c_str(), linenum);
newNode = new AstNode(AST_GENBLOCK);
int num = std::max(children.at(0)->range_left, children.at(0)->range_right) - std::min(children.at(0)->range_left, children.at(0)->range_right) + 1;
int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1;
for (int i = 0; i < num; i++) {
int idx = children.at(0)->range_left > children.at(0)->range_right ? children.at(0)->range_right + i : children.at(0)->range_right - i;
@ -2043,7 +2043,7 @@ skip_dynamic_range_lvalue_expansion:;
if (0) { case AST_GE: const_func = RTLIL::const_ge; }
if (0) { case AST_GT: const_func = RTLIL::const_gt; }
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
int cmp_width = std::max(children[0]->bits.size(), children[1]->bits.size());
int cmp_width = max(children[0]->bits.size(), children[1]->bits.size());
bool cmp_signed = children[0]->is_signed && children[1]->is_signed;
RTLIL::Const y = const_func(children[0]->bitsAsConst(cmp_width, cmp_signed),
children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1);
@ -2236,7 +2236,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);
int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right;
int range_min = std::min(range_left, range_right), range_max = std::max(range_left, range_right);
int range_min = min(range_left, range_right), range_max = max(range_left, range_right);
if (start_addr < 0)
start_addr = range_min;
@ -2720,7 +2720,7 @@ void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
if (mem_size < 0)
mem_size *= -1;
mem_size += std::min(children[1]->range_left, children[1]->range_right) + 1;
mem_size += min(children[1]->range_left, children[1]->range_right) + 1;
addr_bits = 1;
while ((1 << addr_bits) < mem_size)
@ -2756,8 +2756,8 @@ void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
if (!children.at(0)->range_valid)
log_error("Non-constant range in %s:%d (called from %s:%d).\n",
filename.c_str(), linenum, fcall->filename.c_str(), fcall->linenum);
offset = std::min(children.at(0)->range_left, children.at(0)->range_right);
width = std::min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
offset = min(children.at(0)->range_left, children.at(0)->range_right);
width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
}
offset -= variables.at(str).offset;
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits;
@ -2797,7 +2797,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
log_error("Can't determine size of variable %s in %s:%d (called from %s:%d).\n",
child->str.c_str(), child->filename.c_str(), child->linenum, fcall->filename.c_str(), fcall->linenum);
variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1);
variables[child->str].offset = std::min(child->range_left, child->range_right);
variables[child->str].offset = min(child->range_left, child->range_right);
variables[child->str].is_signed = child->is_signed;
if (child->is_input && argidx < fcall->children.size())
variables[child->str].val = fcall->children.at(argidx++)->bitsAsConst(variables[child->str].val.bits.size());
@ -2856,7 +2856,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
if (!range->range_valid)
log_error("Non-constant range in %s:%d (called from %s:%d).\n",
range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum);
int offset = std::min(range->range_left, range->range_right);
int offset = min(range->range_left, range->range_right);
int width = std::abs(range->range_left - range->range_right) + 1;
varinfo_t &v = variables[stmt->children.at(0)->str];
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());

2
frontends/ilang/ilang_parser.y
View file

@ -121,7 +121,7 @@ attr_stmt:
autoidx_stmt:
TOK_AUTOIDX TOK_INT EOL {
autoidx = std::max(autoidx, $2);
autoidx = max(autoidx, $2);
};
wire_stmt:

10
frontends/verific/verific.cc
View file

@ -541,7 +541,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
// log(" importing portbus %s.\n", portbus->Name());
RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size());
wire->start_offset = std::min(portbus->LeftIndex(), portbus->RightIndex());
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
import_attributes(wire->attributes, portbus);
if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN)
@ -580,11 +580,11 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
int bits_in_word = number_of_bits;
FOREACH_PORTREF_OF_NET(net, si, pr) {
if (pr->GetInst()->Type() == OPER_READ_PORT) {
bits_in_word = std::min<int>(bits_in_word, pr->GetInst()->OutputSize());
bits_in_word = min<int>(bits_in_word, pr->GetInst()->OutputSize());
continue;
}
if (pr->GetInst()->Type() == OPER_WRITE_PORT || pr->GetInst()->Type() == OPER_CLOCKED_WRITE_PORT) {
bits_in_word = std::min<int>(bits_in_word, pr->GetInst()->Input2Size());
bits_in_word = min<int>(bits_in_word, pr->GetInst()->Input2Size());
continue;
}
log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n",
@ -630,7 +630,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(netbus->Name()));
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = std::min(netbus->LeftIndex(), netbus->RightIndex());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
import_attributes(wire->attributes, netbus);
for (int i = netbus->LeftIndex();; i += netbus->IsUp() ? +1 : -1) {
@ -752,7 +752,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
if (pr->GetPort()->Bus()) {
port_name = pr->GetPort()->Bus()->Name();
port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
std::min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
}
RTLIL::SigSpec conn;
if (cell->hasPort(RTLIL::escape_id(port_name)))

20
kernel/calc.cc
View file

@ -154,7 +154,7 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1)
{
if (result_len < 0)
result_len = std::max(arg1.bits.size(), arg2.bits.size());
result_len = max(arg1.bits.size(), arg2.bits.size());
extend_u0(arg1, result_len, signed1);
extend_u0(arg2, result_len, signed2);
@ -310,7 +310,7 @@ RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
extend_u0(arg1_ext, std::max(result_len, GetSize(arg1)), signed1);
extend_u0(arg1_ext, max(result_len, GetSize(arg1)), signed1);
return const_shift_worker(arg1_ext, arg2, false, +1, result_len);
}
@ -389,7 +389,7 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len);
int width = std::max(arg1_ext.bits.size(), arg2_ext.bits.size());
int width = max(arg1_ext.bits.size(), arg2_ext.bits.size());
extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2);
@ -423,7 +423,7 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len);
int width = std::max(arg1_ext.bits.size(), arg2_ext.bits.size());
int width = max(arg1_ext.bits.size(), arg2_ext.bits.size());
extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2);
@ -472,21 +472,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
}
RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
}
RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -499,7 +499,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -512,7 +512,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = a.getSign() == BigInteger::negative;
a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -563,7 +563,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
y *= -1;
}
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)

2
kernel/cellaigs.cc
View file

@ -392,7 +392,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in("$eq", "$ne"))
{
int width = std::max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
int width = max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
vector<int> A = mk.inport_vec("\\A", width);
vector<int> B = mk.inport_vec("\\B", width);
int Y = mk.bool_node(false);

2
kernel/driver.cc
View file

@ -404,7 +404,7 @@ int main(int argc, char **argv)
log("%s\n", yosys_version_str);
int64_t total_ns = 0;
std::set<std::tuple<int64_t, int, std::string>> timedat;
std::set<tuple<int64_t, int, std::string>> timedat;
for (auto &it : pass_register)
if (it.second->call_counter) {

4
kernel/macc.h
View file

@ -158,8 +158,8 @@ struct Macc
int max_size = 0, num_bits = 0;
for (auto &port : ports) {
max_size = std::max(max_size, GetSize(port.in_a));
max_size = std::max(max_size, GetSize(port.in_b));
max_size = max(max_size, GetSize(port.in_a));
max_size = max(max_size, GetSize(port.in_b));
}
while (max_size)

28
kernel/rtlil.cc
View file

@ -981,11 +981,11 @@ namespace {
param("\\SIZE");
param("\\OFFSET");
param("\\INIT");
param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS")));
param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS")));
param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS")));
param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS")));
param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS")));
param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
port("\\RD_CLK", param("\\RD_PORTS"));
port("\\RD_EN", param("\\RD_PORTS"));
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
@ -1601,10 +1601,10 @@ DEF_METHOD(LogicNot, 1, "$logic_not")
add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
return sig_y; \
}
DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
DEF_METHOD(Shl, sig_a.size(), "$shl")
DEF_METHOD(Shr, sig_a.size(), "$shr")
DEF_METHOD(Sshl, sig_a.size(), "$sshl")
@ -1619,11 +1619,11 @@ DEF_METHOD(Eqx, 1, "$eqx")
DEF_METHOD(Nex, 1, "$nex")
DEF_METHOD(Ge, 1, "$ge")
DEF_METHOD(Gt, 1, "$gt")
DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
DEF_METHOD(LogicAnd, 1, "$logic_and")
DEF_METHOD(LogicOr, 1, "$logic_or")
#undef DEF_METHOD

2
kernel/satgen.h
View file

@ -980,7 +980,7 @@ struct SatGen
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
}
} else {
int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
int copy_a_bits = min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());

7
kernel/yosys.h
View file

@ -41,6 +41,7 @@
#include <map>
#include <set>
#include <tuple>
#include <vector>
#include <string>
#include <algorithm>
@ -138,8 +139,14 @@ YOSYS_NAMESPACE_BEGIN
using std::vector;
using std::string;
using std::tuple;
using std::pair;
using std::make_tuple;
using std::make_pair;
using std::min;
using std::max;
// A primitive shared string implementation that does not
// move its .c_str() when the object is copied or moved.
struct shared_str {

6
passes/cmds/edgetypes.cc
View file

@ -52,7 +52,7 @@ struct EdgetypePass : public Pass {
for (auto module : design->selected_modules())
{
SigMap sigmap(module);
dict<SigBit, pool<std::tuple<IdString, IdString, int>>> bit_sources, bit_sinks;
dict<SigBit, pool<tuple<IdString, IdString, int>>> bit_sources, bit_sinks;
pool<std::pair<IdString, IdString>> multibit_ports;
for (auto cell : module->selected_cells())
@ -67,9 +67,9 @@ struct EdgetypePass : public Pass {
for (int i = 0; i < GetSize(sig); i++) {
if (cell->output(port_name))
bit_sources[sig[i]].insert(std::tuple<IdString, IdString, int>(cell_type, port_name, i));
bit_sources[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i));
if (cell->input(port_name))
bit_sinks[sig[i]].insert(std::tuple<IdString, IdString, int>(cell_type, port_name, i));
bit_sinks[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i));
}
}

2
passes/cmds/plugin.cc
View file

@ -115,7 +115,7 @@ struct PluginPass : public Pass {
log("\n");
int max_alias_len = 1;
for (auto &it : loaded_plugin_aliases)
max_alias_len = std::max(max_alias_len, GetSize(it.first));
max_alias_len = max(max_alias_len, GetSize(it.first));
for (auto &it : loaded_plugin_aliases)
log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str());
}

20
passes/cmds/qwp.cc
View file

@ -342,8 +342,8 @@ struct QwpWorker
double r = alt_mode ? alt_radius : radius;
if (std::isfinite(v)) {
v = std::min(v, c+r);
v = std::max(v, c-r);
v = min(v, c+r);
v = max(v, c-r);
} else {
v = c;
}
@ -524,15 +524,15 @@ struct QwpWorker
if (rel_pos < 0) {
node.pos = midpos + left_scale*rel_pos;
if (std::isfinite(node.pos)) {
node.pos = std::min(node.pos, midpos);
node.pos = std::max(node.pos, midpos - radius);
node.pos = min(node.pos, midpos);
node.pos = max(node.pos, midpos - radius);
} else
node.pos = midpos - radius/2;
} else {
node.pos = midpos + right_scale*rel_pos;
if (std::isfinite(node.pos)) {
node.pos = std::max(node.pos, midpos);
node.pos = std::min(node.pos, midpos + radius);
node.pos = max(node.pos, midpos);
node.pos = min(node.pos, midpos + radius);
} else
node.pos = midpos + radius/2;
}
@ -666,8 +666,8 @@ struct QwpWorker
double max_value = values.front();
for (auto &v : values) {
min_value = std::min(min_value, v);
max_value = std::max(max_value, v);
min_value = min(min_value, v);
max_value = max(max_value, v);
}
if (fabs(max_value - min_value) < 0.001) {
@ -679,8 +679,8 @@ struct QwpWorker
int max_bucket_val = 0;
for (auto &v : values) {
int idx = std::min(int(GetSize(buckets) * (v - min_value) / (max_value - min_value)), GetSize(buckets)-1);
max_bucket_val = std::max(max_bucket_val, ++buckets.at(idx));
int idx = min(int(GetSize(buckets) * (v - min_value) / (max_value - min_value)), GetSize(buckets)-1);
max_bucket_val = max(max_bucket_val, ++buckets.at(idx));
}
for (int i = 4; i >= 0; i--) {

4
passes/cmds/scc.cc
View file

@ -69,10 +69,10 @@ struct SccWorker
for (auto nextCell : cellToNextCell[cell])
if (cellLabels.count(nextCell) == 0) {
run(nextCell, depth+1, maxDepth);
cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second);
cellLabels[cell].second = min(cellLabels[cell].second, cellLabels[nextCell].second);
} else
if (cellsOnStack.count(nextCell) > 0 && (maxDepth < 0 || cellDepth[nextCell] + maxDepth > depth)) {
cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second);
cellLabels[cell].second = min(cellLabels[cell].second, cellLabels[nextCell].second);
}
if (cellLabels[cell].first == cellLabels[cell].second)

4
passes/cmds/splitnets.cc
View file

@ -140,8 +140,8 @@ struct SplitnetsPass : public Pass {
for (auto wire : module->wires())
if (wire->port_id != 0) {
normalized_port_factor = std::max(normalized_port_factor, wire->port_id+1);
normalized_port_factor = std::max(normalized_port_factor, GetSize(wire)+1);
normalized_port_factor = max(normalized_port_factor, wire->port_id+1);
normalized_port_factor = max(normalized_port_factor, GetSize(wire)+1);
}
for (auto wire : module->wires())

2
passes/cmds/stat.cc
View file

@ -110,7 +110,7 @@ struct statdata_t
int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0;
int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0;
int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in("$mux", "$pmux"))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y")));

2
passes/equiv/equiv_add.cc
View file

@ -63,7 +63,7 @@ struct EquivAddPass : public Pass {
auto port = conn.first;
SigSpec gold_sig = gold_cell->getPort(port);
SigSpec gate_sig = gate_cell->getPort(port);
int width = std::min(GetSize(gold_sig), GetSize(gate_sig));
int width = min(GetSize(gold_sig), GetSize(gate_sig));
if (gold_cell->input(port) && gate_cell->input(port))
{

2
passes/fsm/fsmdata.h
View file

@ -39,7 +39,7 @@ struct FsmData
int state_num_log2 = 0;
for (int i = state_table.size(); i > 0; i = i >> 1)
state_num_log2++;
state_num_log2 = std::max(state_num_log2, 1);
state_num_log2 = max(state_num_log2, 1);
cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits);
cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size());

10
passes/hierarchy/hierarchy.cc
View file

@ -66,7 +66,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
for (auto &conn : i2.second->connections()) {
if (conn.first[0] != '$')
portnames.insert(conn.first);
portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
portwidths[conn.first] = max(portwidths[conn.first], conn.second.size());
}
for (auto &para : i2.second->parameters)
parameters.insert(para.first);
@ -84,8 +84,8 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
for (auto &decl : portdecls)
if (decl.index > 0) {
portwidths[decl.portname] = std::max(portwidths[decl.portname], 1);
portwidths[decl.portname] = std::max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
portwidths[decl.portname] = max(portwidths[decl.portname], 1);
portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname));
if (indices.count(decl.index) > ports.size())
log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size()));
@ -106,7 +106,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
log_assert(!indices.empty());
indices.erase(d.index);
ports[d.index-1] = d;
portwidths[d.portname] = std::max(portwidths[d.portname], 1);
portwidths[d.portname] = max(portwidths[d.portname], 1);
log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname));
goto found_matching_decl;
}
@ -327,7 +327,7 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
db[module] = 0;
for (auto cell : module->cells())
if (design->module(cell->type))
db[module] = std::max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1);
db[module] = max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1);
}
return db.at(module);
}

10
passes/memory/memory_bram.cc
View file

@ -387,9 +387,9 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
if (pi.clkpol > 1)
clkpol_wr_ports.insert(pi.clkpol);
}
clocks_max = std::max(clocks_max, pi.clocks);
clkpol_max = std::max(clkpol_max, pi.clkpol);
transp_max = std::max(transp_max, pi.transp);
clocks_max = max(clocks_max, pi.clocks);
clkpol_max = max(clkpol_max, pi.clkpol);
transp_max = max(transp_max, pi.transp);
}
log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
@ -977,7 +977,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
log("\n");
pool<pair<IdString, int>> failed_brams;
dict<pair<int, int>, std::tuple<int, int, int>> best_rule_cache;
dict<pair<int, int>, tuple<int, int, int>> best_rule_cache;
for (int i = 0; i < GetSize(rules.matches); i++)
{
@ -1078,7 +1078,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
}
log(" Storing for later selection.\n");
best_rule_cache[pair<int, int>(i, vi)] = std::tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]);
best_rule_cache[pair<int, int>(i, vi)] = tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]);
next_match_rule:
if (or_next_if_better || best_rule_cache.empty())

2
passes/memory/memory_collect.cc
View file

@ -64,7 +64,7 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
for (auto &cell_it : module->cells_) {
Cell *cell = cell_it.second;
if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) {
addr_bits = std::max(addr_bits, cell->getParam("\\ABITS").as_int());
addr_bits = max(addr_bits, cell->getParam("\\ABITS").as_int());
memcells.push_back(cell);
}
}

2
passes/memory/memory_share.cc
View file

@ -210,7 +210,7 @@ struct MemoryShareWorker
if (non_feedback_nets.count(sig_data[i]))
goto not_pure_feedback_port;
async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size()));
async_rd_bits[sig_addr].resize(max(async_rd_bits.size(), sig_data.size()));
for (int i = 0; i < int(sig_data.size()); i++)
async_rd_bits[sig_addr][i].insert(sig_data[i]);

2
passes/opt/opt_const.cc
View file

@ -589,7 +589,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec b = cell->getPort("\\B");
if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
int width = max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
}

58
passes/opt/share.cc
View file

@ -113,8 +113,8 @@ struct ShareWorker
static int bits_macc_port(const Macc::port_t &p, int width)
{
if (GetSize(p.in_a) == 0 || GetSize(p.in_b) == 0)
return std::min(std::max(GetSize(p.in_a), GetSize(p.in_b)), width);
return std::min(GetSize(p.in_a), width) * std::min(GetSize(p.in_b), width) / 2;
return min(max(GetSize(p.in_a), GetSize(p.in_b)), width);
return min(GetSize(p.in_a), width) * min(GetSize(p.in_b), width) / 2;
}
static int bits_macc(const Macc &m, int width)
@ -224,13 +224,13 @@ struct ShareWorker
supermacc->ports.push_back(p);
}
int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * std::max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1);
int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1);
for (int i = 0; i < std::min(GetSize(p1.in_a), GetSize(p2.in_a)); i++)
for (int i = 0; i < min(GetSize(p1.in_a), GetSize(p2.in_a)); i++)
if (p1.in_a[i] == p2.in_a[i] && score > 0)
score--;
for (int i = 0; i < std::min(GetSize(p1.in_b), GetSize(p2.in_b)); i++)
for (int i = 0; i < min(GetSize(p1.in_b), GetSize(p2.in_b)); i++)
if (p1.in_b[i] == p2.in_b[i] && score > 0)
score--;
@ -243,7 +243,7 @@ struct ShareWorker
Macc m1(c1), m2(c2), supermacc;
int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y"));
int width = std::max(w1, w2);
int width = max(w1, w2);
m1.optimize(w1);
m2.optimize(w2);
@ -419,8 +419,8 @@ struct ShareWorker
int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
}
return true;
@ -438,9 +438,9 @@ struct ShareWorker
int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false;
if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false;
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
}
return true;
@ -458,15 +458,15 @@ struct ShareWorker
int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
int min1_width = std::min(a1_width, b1_width);
int max1_width = std::max(a1_width, b1_width);
int min1_width = min(a1_width, b1_width);
int max1_width = max(a1_width, b1_width);
int min2_width = std::min(a2_width, b2_width);
int max2_width = std::max(a2_width, b2_width);
int min2_width = min(a2_width, b2_width);
int max2_width = max(a2_width, b2_width);
if (std::max(min1_width, min2_width) > 2 * std::min(min1_width, min2_width)) return false;
if (std::max(max1_width, max2_width) > 2 * std::min(max1_width, max2_width)) return false;
if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
if (max(min1_width, min2_width) > 2 * min(min1_width, min2_width)) return false;
if (max(max1_width, max2_width) > 2 * min(max1_width, max2_width)) return false;
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
}
return true;
@ -475,7 +475,7 @@ struct ShareWorker
if (c1->type == "$macc")
{
if (!config.opt_aggressive)
if (share_macc(c1, c2) > 2 * std::min(bits_macc(c1), bits_macc(c2))) return false;
if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false;
return true;
}
@ -532,8 +532,8 @@ struct ShareWorker
RTLIL::SigSpec a2 = c2->getPort("\\A");
RTLIL::SigSpec y2 = c2->getPort("\\Y");
int a_width = std::max(a1.size(), a2.size());
int y_width = std::max(y1.size(), y2.size());
int a_width = max(a1.size(), a2.size());
int y_width = max(y1.size(), y2.size());
a1.extend_u0(a_width, a_signed);
a2.extend_u0(a_width, a_signed);
@ -563,11 +563,11 @@ struct ShareWorker
if (config.generic_cbin_ops.count(c1->type))
{
int score_unflipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) +
std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int());
int score_unflipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) +
max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int());
int score_flipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) +
std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int());
int score_flipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) +
max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int());
if (score_flipped < score_unflipped)
{
@ -630,13 +630,13 @@ struct ShareWorker
RTLIL::SigSpec b2 = c2->getPort("\\B");
RTLIL::SigSpec y2 = c2->getPort("\\Y");
int a_width = std::max(a1.size(), a2.size());
int b_width = std::max(b1.size(), b2.size());
int y_width = std::max(y1.size(), y2.size());
int a_width = max(a1.size(), a2.size());
int b_width = max(b1.size(), b2.size());
int y_width = max(y1.size(), y2.size());
if (c1->type == "$shr" && a_signed)
{
a_width = std::max(y_width, a_width);
a_width = max(y_width, a_width);
if (a1.size() < y1.size()) a1.extend_u0(y1.size(), true);
if (a2.size() < y2.size()) a2.extend_u0(y2.size(), true);

6
passes/opt/wreduce.cc
View file

@ -188,8 +188,8 @@ struct WreduceWorker
int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1;
if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
max_port_a_size = std::min(max_port_a_size, GetSize(sig));
max_port_b_size = std::min(max_port_b_size, GetSize(sig));
max_port_a_size = min(max_port_a_size, GetSize(sig));
max_port_b_size = min(max_port_b_size, GetSize(sig));
}
bool port_a_signed = false;
@ -228,7 +228,7 @@ struct WreduceWorker
if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A"));
if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B"));
int max_y_size = std::max(a_size, b_size);
int max_y_size = max(a_size, b_size);
if (cell->type == "$add")
max_y_size++;

2
passes/sat/eval.cc
View file

@ -568,7 +568,7 @@ struct EvalPass : public Pass {
if (tab_column_width.size() < row.size())
tab_column_width.resize(row.size());
for (size_t i = 0; i < row.size(); i++)
tab_column_width[i] = std::max(tab_column_width[i], int(row[i].size()));
tab_column_width[i] = max(tab_column_width[i], int(row[i].size()));
}
log("\n");

2
passes/sat/freduce.cc
View file

@ -265,7 +265,7 @@ struct PerformReduction
}
int max_child_depth = 0;
for (auto &bit : drv.second)
max_child_depth = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_depth);
max_child_depth = max(register_cone_worker(celldone, sigdepth, bit), max_child_depth);
sigdepth[out] = max_child_depth + 1;
} else {
pi_bits.push_back(out);

12
passes/sat/sat.cc
View file

@ -606,8 +606,8 @@ struct SatHelper
int maxModelWidth = 10;
for (auto &info : modelInfo) {
maxModelName = std::max(maxModelName, int(info.description.size()));
maxModelWidth = std::max(maxModelWidth, info.width);
maxModelName = max(maxModelName, int(info.description.size()));
maxModelWidth = max(maxModelWidth, info.width);
}
log("\n");
@ -781,9 +781,9 @@ struct SatHelper
wavedata[info.description].first = info.width;
wavedata[info.description].second[info.timestep] = value;
mintime = std::min(mintime, info.timestep);
maxtime = std::max(maxtime, info.timestep);
maxwidth = std::max(maxwidth, info.width);
mintime = min(mintime, info.timestep);
maxtime = max(maxtime, info.timestep);
maxwidth = max(maxwidth, info.width);
}
fprintf(f, "{ \"signal\": [");
@ -1116,7 +1116,7 @@ struct SatPass : public Pass {
continue;
}
if (args[argidx] == "-stepsize" && argidx+1 < args.size()) {
stepsize = std::max(1, atoi(args[++argidx].c_str()));
stepsize = max(1, atoi(args[++argidx].c_str()));
continue;
}
if (args[argidx] == "-ignore_div_by_zero") {

2
passes/techmap/abc.cc
View file

@ -1399,7 +1399,7 @@ struct AbcPass : public Pass {
std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
typedef std::tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;

6
passes/techmap/alumacc.cc
View file

@ -40,7 +40,7 @@ struct AlumaccWorker
{
std::vector<RTLIL::Cell*> cells;
RTLIL::SigSpec a, b, c, y;
std::vector<std::tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
bool is_signed, invert_b;
RTLIL::Cell *alu_cell;
@ -138,7 +138,7 @@ struct AlumaccWorker
n->users = 0;
for (auto bit : n->y)
n->users = std::max(n->users, bit_users.at(bit) - 1);
n->users = max(n->users, bit_users.at(bit) - 1);
if (cell->type.in("$pos", "$neg"))
{
@ -409,7 +409,7 @@ struct AlumaccWorker
n->a = A;
n->b = B;
n->c = RTLIL::S1;
n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B)));
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);

4
passes/techmap/dffinit.cc
View file

@ -68,7 +68,7 @@ struct DffinitPass : public Pass {
for (auto wire : module->selected_wires()) {
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (wire->port_output)
@ -116,7 +116,7 @@ struct DffinitPass : public Pass {
if (wire->attributes.count("\\init")) {
Const &value = wire->attributes.at("\\init");
bool do_cleanup = true;
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) {
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (cleanup_bits.count(bit) || !used_bits.count(bit))
value[i] = State::Sx;

2
passes/techmap/extract.cc
View file

@ -130,7 +130,7 @@ public:
RTLIL::SigSpec needleSig = conn.second;
RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))

2
passes/techmap/maccmap.cc
View file

@ -134,7 +134,7 @@ struct MaccmapWorker
}
return retval;
#else
return std::max(n - 1, 0);
return max(n - 1, 0);
#endif
}

6
passes/techmap/muxcover.cc
View file

@ -49,8 +49,8 @@ struct MuxcoverWorker
vector<tree_t> tree_list;
dict<std::tuple<SigBit, SigBit, SigBit>, std::tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
dict<SigBit, std::tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
dict<tuple<SigBit, SigBit, SigBit>, tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
dict<SigBit, tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
int decode_mux_counter;
bool use_mux4;
@ -142,7 +142,7 @@ struct MuxcoverWorker
if (A == B)
return 0;
std::tuple<SigBit, SigBit, SigBit> key(A, B, sel);
tuple<SigBit, SigBit, SigBit> key(A, B, sel);
if (decode_mux_cache.count(key) == 0) {
auto &entry = decode_mux_cache[key];
std::get<0>(entry) = module->addWire(NEW_ID);

2
passes/techmap/simplemap.cc
View file

@ -247,7 +247,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
bool is_ne = cell->type == "$ne" || cell->type == "$nex";
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
simplemap_bitop(module, xor_cell);

2
passes/tests/test_cell.cc
View file

@ -256,7 +256,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
case 2:
n = xorshift32(GetSize(sig));
m = xorshift32(GetSize(sig));
for (int i = std::min(n, m); i < std::max(n, m); i++)
for (int i = min(n, m); i < max(n, m); i++)
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
break;
}