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Import more std:: stuff into Yosys namespace
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39 changed files with 168 additions and 161 deletions
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@ -247,7 +247,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
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bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
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bool is_ne = cell->type == "$ne" || cell->type == "$nex";
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RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
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RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
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RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
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xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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simplemap_bitop(module, xor_cell);
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