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Import more std:: stuff into Yosys namespace

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This commit is contained in:
Clifford Wolf 2015-10-25 19:30:49 +01:00
parent da923c198e
commit 207736b4ee
39 changed files with 168 additions and 161 deletions
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2
passes/techmap/extract.cc
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@ -130,7 +130,7 @@ public:
RTLIL::SigSpec needleSig = conn.second;
RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))