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Import more std:: stuff into Yosys namespace

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This commit is contained in:
Clifford Wolf 2015-10-25 19:30:49 +01:00
parent da923c198e
commit 207736b4ee
39 changed files with 168 additions and 161 deletions
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2
passes/techmap/abc.cc
View file

@ -1399,7 +1399,7 @@ struct AbcPass : public Pass {
std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
typedef std::tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;

6
passes/techmap/alumacc.cc
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@ -40,7 +40,7 @@ struct AlumaccWorker
{
std::vector<RTLIL::Cell*> cells;
RTLIL::SigSpec a, b, c, y;
std::vector<std::tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
bool is_signed, invert_b;
RTLIL::Cell *alu_cell;
@ -138,7 +138,7 @@ struct AlumaccWorker
n->users = 0;
for (auto bit : n->y)
n->users = std::max(n->users, bit_users.at(bit) - 1);
n->users = max(n->users, bit_users.at(bit) - 1);
if (cell->type.in("$pos", "$neg"))
{
@ -409,7 +409,7 @@ struct AlumaccWorker
n->a = A;
n->b = B;
n->c = RTLIL::S1;
n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B)));
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);

4
passes/techmap/dffinit.cc
View file

@ -68,7 +68,7 @@ struct DffinitPass : public Pass {
for (auto wire : module->selected_wires()) {
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (wire->port_output)
@ -116,7 +116,7 @@ struct DffinitPass : public Pass {
if (wire->attributes.count("\\init")) {
Const &value = wire->attributes.at("\\init");
bool do_cleanup = true;
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) {
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (cleanup_bits.count(bit) || !used_bits.count(bit))
value[i] = State::Sx;

2
passes/techmap/extract.cc
View file

@ -130,7 +130,7 @@ public:
RTLIL::SigSpec needleSig = conn.second;
RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))

2
passes/techmap/maccmap.cc
View file

@ -134,7 +134,7 @@ struct MaccmapWorker
}
return retval;
#else
return std::max(n - 1, 0);
return max(n - 1, 0);
#endif
}

6
passes/techmap/muxcover.cc
View file

@ -49,8 +49,8 @@ struct MuxcoverWorker
vector<tree_t> tree_list;
dict<std::tuple<SigBit, SigBit, SigBit>, std::tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
dict<SigBit, std::tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
dict<tuple<SigBit, SigBit, SigBit>, tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
dict<SigBit, tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
int decode_mux_counter;
bool use_mux4;
@ -142,7 +142,7 @@ struct MuxcoverWorker
if (A == B)
return 0;
std::tuple<SigBit, SigBit, SigBit> key(A, B, sel);
tuple<SigBit, SigBit, SigBit> key(A, B, sel);
if (decode_mux_cache.count(key) == 0) {
auto &entry = decode_mux_cache[key];
std::get<0>(entry) = module->addWire(NEW_ID);

2
passes/techmap/simplemap.cc
View file

@ -247,7 +247,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
bool is_ne = cell->type == "$ne" || cell->type == "$nex";
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
simplemap_bitop(module, xor_cell);