mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 00:55:32 +00:00
Import more std:: stuff into Yosys namespace
This commit is contained in:
Clifford Wolf
parent
da923c198e
commit
207736b4ee
39 changed files with 168 additions and 161 deletions
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@ -52,7 +52,7 @@ struct EdgetypePass : public Pass {
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, pool<std::tuple<IdString, IdString, int>>> bit_sources, bit_sinks;
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dict<SigBit, pool<tuple<IdString, IdString, int>>> bit_sources, bit_sinks;
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pool<std::pair<IdString, IdString>> multibit_ports;
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for (auto cell : module->selected_cells())
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@ -67,9 +67,9 @@ struct EdgetypePass : public Pass {
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for (int i = 0; i < GetSize(sig); i++) {
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if (cell->output(port_name))
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bit_sources[sig[i]].insert(std::tuple<IdString, IdString, int>(cell_type, port_name, i));
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bit_sources[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i));
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if (cell->input(port_name))
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bit_sinks[sig[i]].insert(std::tuple<IdString, IdString, int>(cell_type, port_name, i));
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bit_sinks[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i));
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}
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}
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@ -115,7 +115,7 @@ struct PluginPass : public Pass {
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log("\n");
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int max_alias_len = 1;
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for (auto &it : loaded_plugin_aliases)
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max_alias_len = std::max(max_alias_len, GetSize(it.first));
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max_alias_len = max(max_alias_len, GetSize(it.first));
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for (auto &it : loaded_plugin_aliases)
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log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str());
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}
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@ -342,8 +342,8 @@ struct QwpWorker
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double r = alt_mode ? alt_radius : radius;
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if (std::isfinite(v)) {
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v = std::min(v, c+r);
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v = std::max(v, c-r);
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v = min(v, c+r);
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v = max(v, c-r);
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} else {
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v = c;
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}
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@ -524,15 +524,15 @@ struct QwpWorker
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if (rel_pos < 0) {
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node.pos = midpos + left_scale*rel_pos;
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if (std::isfinite(node.pos)) {
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node.pos = std::min(node.pos, midpos);
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node.pos = std::max(node.pos, midpos - radius);
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node.pos = min(node.pos, midpos);
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node.pos = max(node.pos, midpos - radius);
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} else
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node.pos = midpos - radius/2;
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} else {
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node.pos = midpos + right_scale*rel_pos;
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if (std::isfinite(node.pos)) {
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node.pos = std::max(node.pos, midpos);
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node.pos = std::min(node.pos, midpos + radius);
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node.pos = max(node.pos, midpos);
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node.pos = min(node.pos, midpos + radius);
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} else
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node.pos = midpos + radius/2;
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}
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@ -666,8 +666,8 @@ struct QwpWorker
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double max_value = values.front();
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for (auto &v : values) {
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min_value = std::min(min_value, v);
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max_value = std::max(max_value, v);
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min_value = min(min_value, v);
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max_value = max(max_value, v);
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}
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if (fabs(max_value - min_value) < 0.001) {
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@ -679,8 +679,8 @@ struct QwpWorker
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int max_bucket_val = 0;
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for (auto &v : values) {
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int idx = std::min(int(GetSize(buckets) * (v - min_value) / (max_value - min_value)), GetSize(buckets)-1);
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max_bucket_val = std::max(max_bucket_val, ++buckets.at(idx));
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int idx = min(int(GetSize(buckets) * (v - min_value) / (max_value - min_value)), GetSize(buckets)-1);
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max_bucket_val = max(max_bucket_val, ++buckets.at(idx));
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}
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for (int i = 4; i >= 0; i--) {
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@ -69,10 +69,10 @@ struct SccWorker
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for (auto nextCell : cellToNextCell[cell])
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if (cellLabels.count(nextCell) == 0) {
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run(nextCell, depth+1, maxDepth);
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cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second);
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cellLabels[cell].second = min(cellLabels[cell].second, cellLabels[nextCell].second);
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} else
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if (cellsOnStack.count(nextCell) > 0 && (maxDepth < 0 || cellDepth[nextCell] + maxDepth > depth)) {
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cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second);
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cellLabels[cell].second = min(cellLabels[cell].second, cellLabels[nextCell].second);
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}
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if (cellLabels[cell].first == cellLabels[cell].second)
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@ -140,8 +140,8 @@ struct SplitnetsPass : public Pass {
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for (auto wire : module->wires())
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if (wire->port_id != 0) {
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normalized_port_factor = std::max(normalized_port_factor, wire->port_id+1);
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normalized_port_factor = std::max(normalized_port_factor, GetSize(wire)+1);
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normalized_port_factor = max(normalized_port_factor, wire->port_id+1);
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normalized_port_factor = max(normalized_port_factor, GetSize(wire)+1);
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}
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for (auto wire : module->wires())
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@ -110,7 +110,7 @@ struct statdata_t
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int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0;
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int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0;
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int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0;
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cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
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cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
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}
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else if (cell_type.in("$mux", "$pmux"))
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cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y")));
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@ -63,7 +63,7 @@ struct EquivAddPass : public Pass {
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auto port = conn.first;
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SigSpec gold_sig = gold_cell->getPort(port);
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SigSpec gate_sig = gate_cell->getPort(port);
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int width = std::min(GetSize(gold_sig), GetSize(gate_sig));
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int width = min(GetSize(gold_sig), GetSize(gate_sig));
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if (gold_cell->input(port) && gate_cell->input(port))
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{
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@ -39,7 +39,7 @@ struct FsmData
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int state_num_log2 = 0;
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for (int i = state_table.size(); i > 0; i = i >> 1)
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state_num_log2++;
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state_num_log2 = std::max(state_num_log2, 1);
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state_num_log2 = max(state_num_log2, 1);
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cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits);
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cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size());
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@ -66,7 +66,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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for (auto &conn : i2.second->connections()) {
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if (conn.first[0] != '$')
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portnames.insert(conn.first);
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portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
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portwidths[conn.first] = max(portwidths[conn.first], conn.second.size());
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}
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for (auto ¶ : i2.second->parameters)
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parameters.insert(para.first);
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@ -84,8 +84,8 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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for (auto &decl : portdecls)
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if (decl.index > 0) {
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portwidths[decl.portname] = std::max(portwidths[decl.portname], 1);
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portwidths[decl.portname] = std::max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
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portwidths[decl.portname] = max(portwidths[decl.portname], 1);
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portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
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log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname));
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if (indices.count(decl.index) > ports.size())
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log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size()));
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@ -106,7 +106,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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log_assert(!indices.empty());
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indices.erase(d.index);
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ports[d.index-1] = d;
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portwidths[d.portname] = std::max(portwidths[d.portname], 1);
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portwidths[d.portname] = max(portwidths[d.portname], 1);
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log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname));
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goto found_matching_decl;
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}
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@ -327,7 +327,7 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
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db[module] = 0;
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for (auto cell : module->cells())
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if (design->module(cell->type))
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db[module] = std::max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1);
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db[module] = max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1);
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}
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return db.at(module);
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}
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@ -387,9 +387,9 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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if (pi.clkpol > 1)
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clkpol_wr_ports.insert(pi.clkpol);
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}
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clocks_max = std::max(clocks_max, pi.clocks);
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clkpol_max = std::max(clkpol_max, pi.clkpol);
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transp_max = std::max(transp_max, pi.transp);
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clocks_max = max(clocks_max, pi.clocks);
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clkpol_max = max(clkpol_max, pi.clkpol);
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transp_max = max(transp_max, pi.transp);
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}
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log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
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@ -977,7 +977,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
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log("\n");
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pool<pair<IdString, int>> failed_brams;
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dict<pair<int, int>, std::tuple<int, int, int>> best_rule_cache;
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dict<pair<int, int>, tuple<int, int, int>> best_rule_cache;
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for (int i = 0; i < GetSize(rules.matches); i++)
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{
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@ -1078,7 +1078,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
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}
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log(" Storing for later selection.\n");
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best_rule_cache[pair<int, int>(i, vi)] = std::tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]);
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best_rule_cache[pair<int, int>(i, vi)] = tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]);
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next_match_rule:
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if (or_next_if_better || best_rule_cache.empty())
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@ -64,7 +64,7 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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for (auto &cell_it : module->cells_) {
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Cell *cell = cell_it.second;
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if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) {
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addr_bits = std::max(addr_bits, cell->getParam("\\ABITS").as_int());
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addr_bits = max(addr_bits, cell->getParam("\\ABITS").as_int());
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memcells.push_back(cell);
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}
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}
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@ -210,7 +210,7 @@ struct MemoryShareWorker
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if (non_feedback_nets.count(sig_data[i]))
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goto not_pure_feedback_port;
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async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size()));
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async_rd_bits[sig_addr].resize(max(async_rd_bits.size(), sig_data.size()));
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for (int i = 0; i < int(sig_data.size()); i++)
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async_rd_bits[sig_addr][i].insert(sig_data[i]);
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@ -589,7 +589,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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RTLIL::SigSpec b = cell->getPort("\\B");
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if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
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int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
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int width = max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
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a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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}
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@ -113,8 +113,8 @@ struct ShareWorker
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static int bits_macc_port(const Macc::port_t &p, int width)
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{
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if (GetSize(p.in_a) == 0 || GetSize(p.in_b) == 0)
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return std::min(std::max(GetSize(p.in_a), GetSize(p.in_b)), width);
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return std::min(GetSize(p.in_a), width) * std::min(GetSize(p.in_b), width) / 2;
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return min(max(GetSize(p.in_a), GetSize(p.in_b)), width);
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return min(GetSize(p.in_a), width) * min(GetSize(p.in_b), width) / 2;
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}
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static int bits_macc(const Macc &m, int width)
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@ -224,13 +224,13 @@ struct ShareWorker
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supermacc->ports.push_back(p);
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}
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int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * std::max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1);
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int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1);
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for (int i = 0; i < std::min(GetSize(p1.in_a), GetSize(p2.in_a)); i++)
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for (int i = 0; i < min(GetSize(p1.in_a), GetSize(p2.in_a)); i++)
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if (p1.in_a[i] == p2.in_a[i] && score > 0)
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score--;
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for (int i = 0; i < std::min(GetSize(p1.in_b), GetSize(p2.in_b)); i++)
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for (int i = 0; i < min(GetSize(p1.in_b), GetSize(p2.in_b)); i++)
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if (p1.in_b[i] == p2.in_b[i] && score > 0)
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score--;
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@ -243,7 +243,7 @@ struct ShareWorker
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Macc m1(c1), m2(c2), supermacc;
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int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y"));
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int width = std::max(w1, w2);
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int width = max(w1, w2);
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m1.optimize(w1);
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m2.optimize(w2);
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@ -419,8 +419,8 @@ struct ShareWorker
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
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if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
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if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
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}
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return true;
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@ -438,9 +438,9 @@ struct ShareWorker
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
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if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
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if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
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if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false;
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if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
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}
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return true;
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@ -458,15 +458,15 @@ struct ShareWorker
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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int min1_width = std::min(a1_width, b1_width);
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int max1_width = std::max(a1_width, b1_width);
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int min1_width = min(a1_width, b1_width);
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int max1_width = max(a1_width, b1_width);
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int min2_width = std::min(a2_width, b2_width);
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int max2_width = std::max(a2_width, b2_width);
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int min2_width = min(a2_width, b2_width);
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int max2_width = max(a2_width, b2_width);
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if (std::max(min1_width, min2_width) > 2 * std::min(min1_width, min2_width)) return false;
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if (std::max(max1_width, max2_width) > 2 * std::min(max1_width, max2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
|
||||
if (max(min1_width, min2_width) > 2 * min(min1_width, min2_width)) return false;
|
||||
if (max(max1_width, max2_width) > 2 * min(max1_width, max2_width)) return false;
|
||||
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
|
@ -475,7 +475,7 @@ struct ShareWorker
|
|||
if (c1->type == "$macc")
|
||||
{
|
||||
if (!config.opt_aggressive)
|
||||
if (share_macc(c1, c2) > 2 * std::min(bits_macc(c1), bits_macc(c2))) return false;
|
||||
if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -532,8 +532,8 @@ struct ShareWorker
|
|||
RTLIL::SigSpec a2 = c2->getPort("\\A");
|
||||
RTLIL::SigSpec y2 = c2->getPort("\\Y");
|
||||
|
||||
int a_width = std::max(a1.size(), a2.size());
|
||||
int y_width = std::max(y1.size(), y2.size());
|
||||
int a_width = max(a1.size(), a2.size());
|
||||
int y_width = max(y1.size(), y2.size());
|
||||
|
||||
a1.extend_u0(a_width, a_signed);
|
||||
a2.extend_u0(a_width, a_signed);
|
||||
|
|
@ -563,11 +563,11 @@ struct ShareWorker
|
|||
|
||||
if (config.generic_cbin_ops.count(c1->type))
|
||||
{
|
||||
int score_unflipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) +
|
||||
std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int());
|
||||
int score_unflipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) +
|
||||
max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int());
|
||||
|
||||
int score_flipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) +
|
||||
std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int());
|
||||
int score_flipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) +
|
||||
max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int());
|
||||
|
||||
if (score_flipped < score_unflipped)
|
||||
{
|
||||
|
|
@ -630,13 +630,13 @@ struct ShareWorker
|
|||
RTLIL::SigSpec b2 = c2->getPort("\\B");
|
||||
RTLIL::SigSpec y2 = c2->getPort("\\Y");
|
||||
|
||||
int a_width = std::max(a1.size(), a2.size());
|
||||
int b_width = std::max(b1.size(), b2.size());
|
||||
int y_width = std::max(y1.size(), y2.size());
|
||||
int a_width = max(a1.size(), a2.size());
|
||||
int b_width = max(b1.size(), b2.size());
|
||||
int y_width = max(y1.size(), y2.size());
|
||||
|
||||
if (c1->type == "$shr" && a_signed)
|
||||
{
|
||||
a_width = std::max(y_width, a_width);
|
||||
a_width = max(y_width, a_width);
|
||||
|
||||
if (a1.size() < y1.size()) a1.extend_u0(y1.size(), true);
|
||||
if (a2.size() < y2.size()) a2.extend_u0(y2.size(), true);
|
||||
|
|
|
|||
|
|
@ -188,8 +188,8 @@ struct WreduceWorker
|
|||
int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1;
|
||||
|
||||
if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
|
||||
max_port_a_size = std::min(max_port_a_size, GetSize(sig));
|
||||
max_port_b_size = std::min(max_port_b_size, GetSize(sig));
|
||||
max_port_a_size = min(max_port_a_size, GetSize(sig));
|
||||
max_port_b_size = min(max_port_b_size, GetSize(sig));
|
||||
}
|
||||
|
||||
bool port_a_signed = false;
|
||||
|
|
@ -228,7 +228,7 @@ struct WreduceWorker
|
|||
if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A"));
|
||||
if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B"));
|
||||
|
||||
int max_y_size = std::max(a_size, b_size);
|
||||
int max_y_size = max(a_size, b_size);
|
||||
|
||||
if (cell->type == "$add")
|
||||
max_y_size++;
|
||||
|
|
|
|||
|
|
@ -568,7 +568,7 @@ struct EvalPass : public Pass {
|
|||
if (tab_column_width.size() < row.size())
|
||||
tab_column_width.resize(row.size());
|
||||
for (size_t i = 0; i < row.size(); i++)
|
||||
tab_column_width[i] = std::max(tab_column_width[i], int(row[i].size()));
|
||||
tab_column_width[i] = max(tab_column_width[i], int(row[i].size()));
|
||||
}
|
||||
|
||||
log("\n");
|
||||
|
|
|
|||
|
|
@ -265,7 +265,7 @@ struct PerformReduction
|
|||
}
|
||||
int max_child_depth = 0;
|
||||
for (auto &bit : drv.second)
|
||||
max_child_depth = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_depth);
|
||||
max_child_depth = max(register_cone_worker(celldone, sigdepth, bit), max_child_depth);
|
||||
sigdepth[out] = max_child_depth + 1;
|
||||
} else {
|
||||
pi_bits.push_back(out);
|
||||
|
|
|
|||
|
|
@ -606,8 +606,8 @@ struct SatHelper
|
|||
int maxModelWidth = 10;
|
||||
|
||||
for (auto &info : modelInfo) {
|
||||
maxModelName = std::max(maxModelName, int(info.description.size()));
|
||||
maxModelWidth = std::max(maxModelWidth, info.width);
|
||||
maxModelName = max(maxModelName, int(info.description.size()));
|
||||
maxModelWidth = max(maxModelWidth, info.width);
|
||||
}
|
||||
|
||||
log("\n");
|
||||
|
|
@ -781,9 +781,9 @@ struct SatHelper
|
|||
|
||||
wavedata[info.description].first = info.width;
|
||||
wavedata[info.description].second[info.timestep] = value;
|
||||
mintime = std::min(mintime, info.timestep);
|
||||
maxtime = std::max(maxtime, info.timestep);
|
||||
maxwidth = std::max(maxwidth, info.width);
|
||||
mintime = min(mintime, info.timestep);
|
||||
maxtime = max(maxtime, info.timestep);
|
||||
maxwidth = max(maxwidth, info.width);
|
||||
}
|
||||
|
||||
fprintf(f, "{ \"signal\": [");
|
||||
|
|
@ -1116,7 +1116,7 @@ struct SatPass : public Pass {
|
|||
continue;
|
||||
}
|
||||
if (args[argidx] == "-stepsize" && argidx+1 < args.size()) {
|
||||
stepsize = std::max(1, atoi(args[++argidx].c_str()));
|
||||
stepsize = max(1, atoi(args[++argidx].c_str()));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-ignore_div_by_zero") {
|
||||
|
|
|
|||
|
|
@ -1399,7 +1399,7 @@ struct AbcPass : public Pass {
|
|||
std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
|
||||
std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
|
||||
|
||||
typedef std::tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
|
||||
typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
|
||||
std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
|
||||
std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ struct AlumaccWorker
|
|||
{
|
||||
std::vector<RTLIL::Cell*> cells;
|
||||
RTLIL::SigSpec a, b, c, y;
|
||||
std::vector<std::tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
|
||||
std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
|
||||
bool is_signed, invert_b;
|
||||
|
||||
RTLIL::Cell *alu_cell;
|
||||
|
|
@ -138,7 +138,7 @@ struct AlumaccWorker
|
|||
n->users = 0;
|
||||
|
||||
for (auto bit : n->y)
|
||||
n->users = std::max(n->users, bit_users.at(bit) - 1);
|
||||
n->users = max(n->users, bit_users.at(bit) - 1);
|
||||
|
||||
if (cell->type.in("$pos", "$neg"))
|
||||
{
|
||||
|
|
@ -409,7 +409,7 @@ struct AlumaccWorker
|
|||
n->a = A;
|
||||
n->b = B;
|
||||
n->c = RTLIL::S1;
|
||||
n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B)));
|
||||
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
|
||||
n->is_signed = is_signed;
|
||||
n->invert_b = true;
|
||||
sig_alu[RTLIL::SigSig(A, B)].insert(n);
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ struct DffinitPass : public Pass {
|
|||
for (auto wire : module->selected_wires()) {
|
||||
if (wire->attributes.count("\\init")) {
|
||||
Const value = wire->attributes.at("\\init");
|
||||
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
|
||||
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
|
||||
init_bits[sigmap(SigBit(wire, i))] = value[i];
|
||||
}
|
||||
if (wire->port_output)
|
||||
|
|
@ -116,7 +116,7 @@ struct DffinitPass : public Pass {
|
|||
if (wire->attributes.count("\\init")) {
|
||||
Const &value = wire->attributes.at("\\init");
|
||||
bool do_cleanup = true;
|
||||
for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) {
|
||||
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
|
||||
SigBit bit = sigmap(SigBit(wire, i));
|
||||
if (cleanup_bits.count(bit) || !used_bits.count(bit))
|
||||
value[i] = State::Sx;
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ public:
|
|||
RTLIL::SigSpec needleSig = conn.second;
|
||||
RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
|
||||
|
||||
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
|
||||
for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) {
|
||||
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
|
||||
if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
|
||||
if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@ struct MaccmapWorker
|
|||
}
|
||||
return retval;
|
||||
#else
|
||||
return std::max(n - 1, 0);
|
||||
return max(n - 1, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -49,8 +49,8 @@ struct MuxcoverWorker
|
|||
|
||||
vector<tree_t> tree_list;
|
||||
|
||||
dict<std::tuple<SigBit, SigBit, SigBit>, std::tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
|
||||
dict<SigBit, std::tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
|
||||
dict<tuple<SigBit, SigBit, SigBit>, tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache;
|
||||
dict<SigBit, tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache;
|
||||
int decode_mux_counter;
|
||||
|
||||
bool use_mux4;
|
||||
|
|
@ -142,7 +142,7 @@ struct MuxcoverWorker
|
|||
if (A == B)
|
||||
return 0;
|
||||
|
||||
std::tuple<SigBit, SigBit, SigBit> key(A, B, sel);
|
||||
tuple<SigBit, SigBit, SigBit> key(A, B, sel);
|
||||
if (decode_mux_cache.count(key) == 0) {
|
||||
auto &entry = decode_mux_cache[key];
|
||||
std::get<0>(entry) = module->addWire(NEW_ID);
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
|
|||
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
|
||||
bool is_ne = cell->type == "$ne" || cell->type == "$nex";
|
||||
|
||||
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
|
||||
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
|
||||
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
|
||||
xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
|
||||
simplemap_bitop(module, xor_cell);
|
||||
|
|
|
|||
|
|
@ -256,7 +256,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
|
|||
case 2:
|
||||
n = xorshift32(GetSize(sig));
|
||||
m = xorshift32(GetSize(sig));
|
||||
for (int i = std::min(n, m); i < std::max(n, m); i++)
|
||||
for (int i = min(n, m); i < max(n, m); i++)
|
||||
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue