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Import more std:: stuff into Yosys namespace

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This commit is contained in:
Clifford Wolf 2015-10-25 19:30:49 +01:00
parent da923c198e
commit 207736b4ee
39 changed files with 168 additions and 161 deletions
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20
kernel/calc.cc
View file

@ -154,7 +154,7 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1)
{
if (result_len < 0)
result_len = std::max(arg1.bits.size(), arg2.bits.size());
result_len = max(arg1.bits.size(), arg2.bits.size());
extend_u0(arg1, result_len, signed1);
extend_u0(arg2, result_len, signed2);
@ -310,7 +310,7 @@ RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
extend_u0(arg1_ext, std::max(result_len, GetSize(arg1)), signed1);
extend_u0(arg1_ext, max(result_len, GetSize(arg1)), signed1);
return const_shift_worker(arg1_ext, arg2, false, +1, result_len);
}
@ -389,7 +389,7 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len);
int width = std::max(arg1_ext.bits.size(), arg2_ext.bits.size());
int width = max(arg1_ext.bits.size(), arg2_ext.bits.size());
extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2);
@ -423,7 +423,7 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len);
int width = std::max(arg1_ext.bits.size(), arg2_ext.bits.size());
int width = max(arg1_ext.bits.size(), arg2_ext.bits.size());
extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2);
@ -472,21 +472,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
}
RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
}
RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -499,7 +499,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -512,7 +512,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = a.getSign() == BigInteger::negative;
a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -563,7 +563,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
y *= -1;
}
return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)

2
kernel/cellaigs.cc
View file

@ -392,7 +392,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in("$eq", "$ne"))
{
int width = std::max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
int width = max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
vector<int> A = mk.inport_vec("\\A", width);
vector<int> B = mk.inport_vec("\\B", width);
int Y = mk.bool_node(false);

2
kernel/driver.cc
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@ -404,7 +404,7 @@ int main(int argc, char **argv)
log("%s\n", yosys_version_str);
int64_t total_ns = 0;
std::set<std::tuple<int64_t, int, std::string>> timedat;
std::set<tuple<int64_t, int, std::string>> timedat;
for (auto &it : pass_register)
if (it.second->call_counter) {

4
kernel/macc.h
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@ -158,8 +158,8 @@ struct Macc
int max_size = 0, num_bits = 0;
for (auto &port : ports) {
max_size = std::max(max_size, GetSize(port.in_a));
max_size = std::max(max_size, GetSize(port.in_b));
max_size = max(max_size, GetSize(port.in_a));
max_size = max(max_size, GetSize(port.in_b));
}
while (max_size)

28
kernel/rtlil.cc
View file

@ -981,11 +981,11 @@ namespace {
param("\\SIZE");
param("\\OFFSET");
param("\\INIT");
param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS")));
param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS")));
param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS")));
param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS")));
param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS")));
param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
port("\\RD_CLK", param("\\RD_PORTS"));
port("\\RD_EN", param("\\RD_PORTS"));
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
@ -1601,10 +1601,10 @@ DEF_METHOD(LogicNot, 1, "$logic_not")
add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
return sig_y; \
}
DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
DEF_METHOD(Shl, sig_a.size(), "$shl")
DEF_METHOD(Shr, sig_a.size(), "$shr")
DEF_METHOD(Sshl, sig_a.size(), "$sshl")
@ -1619,11 +1619,11 @@ DEF_METHOD(Eqx, 1, "$eqx")
DEF_METHOD(Nex, 1, "$nex")
DEF_METHOD(Ge, 1, "$ge")
DEF_METHOD(Gt, 1, "$gt")
DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
DEF_METHOD(LogicAnd, 1, "$logic_and")
DEF_METHOD(LogicOr, 1, "$logic_or")
#undef DEF_METHOD

2
kernel/satgen.h
View file

@ -980,7 +980,7 @@ struct SatGen
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
}
} else {
int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
int copy_a_bits = min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());

7
kernel/yosys.h
View file

@ -41,6 +41,7 @@
#include <map>
#include <set>
#include <tuple>
#include <vector>
#include <string>
#include <algorithm>
@ -138,8 +139,14 @@ YOSYS_NAMESPACE_BEGIN
using std::vector;
using std::string;
using std::tuple;
using std::pair;
using std::make_tuple;
using std::make_pair;
using std::min;
using std::max;
// A primitive shared string implementation that does not
// move its .c_str() when the object is copied or moved.
struct shared_str {