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gatemate: Add CC_FIFO_40K simulation model
This commit is contained in:
Patrick Urban
parent
c244a7161b
commit
2004a9ff4a
2 changed files with 387 additions and 67 deletions
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@ -131,70 +131,3 @@ module CC_USR_RSTN (
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output USR_RSTN
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);
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endmodule
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(* blackbox *)
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module CC_FIFO_40K (
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output A_ECC_1B_ERR,
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output B_ECC_1B_ERR,
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output A_ECC_2B_ERR,
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output B_ECC_2B_ERR,
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// FIFO pop port
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output [39:0] A_DO,
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output [39:0] B_DO,
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(* clkbuf_sink *)
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input A_CLK,
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input A_EN,
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// FIFO push port
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input [39:0] A_DI,
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input [39:0] B_DI,
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input [39:0] A_BM,
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input [39:0] B_BM,
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(* clkbuf_sink *)
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input B_CLK,
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input B_EN,
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input B_WE,
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// FIFO control
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input F_RST_N,
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input [12:0] F_ALMOST_FULL_OFFSET,
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input [12:0] F_ALMOST_EMPTY_OFFSET,
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// FIFO status signals
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output F_FULL,
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output F_EMPTY,
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output F_ALMOST_FULL,
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output F_ALMOST_EMPTY,
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output F_RD_ERROR,
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output F_WR_ERROR,
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output [15:0] F_RD_PTR,
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output [15:0] F_WR_PTR
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);
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// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
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parameter LOC = "UNPLACED";
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// Offset configuration
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parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
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parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;
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// Port Widths
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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// RAM and Write Modes
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parameter RAM_MODE = "SDP"; // "TPD" or "SDP"
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parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"
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// Inverting Control Pins
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parameter A_CLK_INV = 1'b0;
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parameter B_CLK_INV = 1'b0;
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parameter A_EN_INV = 1'b0;
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parameter B_EN_INV = 1'b0;
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parameter A_WE_INV = 1'b0;
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parameter B_WE_INV = 1'b0;
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// Output Register
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parameter A_DO_REG = 1'b0;
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parameter B_DO_REG = 1'b0;
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// Error Checking and Correction
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parameter A_ECC_EN = 1'b0;
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parameter B_ECC_EN = 1'b0;
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endmodule
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@ -1410,6 +1410,393 @@ module CC_BRAM_40K (
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endgenerate
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endmodule
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module CC_FIFO_40K (
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output A_ECC_1B_ERR,
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output B_ECC_1B_ERR,
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output A_ECC_2B_ERR,
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output B_ECC_2B_ERR,
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// FIFO pop port
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output [39:0] A_DO,
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output [39:0] B_DO,
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(* clkbuf_sink *)
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input A_CLK,
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input A_EN,
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// FIFO push port
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input [39:0] A_DI,
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input [39:0] B_DI,
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input [39:0] A_BM,
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input [39:0] B_BM,
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(* clkbuf_sink *)
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input B_CLK,
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input B_EN,
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input B_WE,
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// FIFO control
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input F_RST_N,
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input [14:0] F_ALMOST_FULL_OFFSET,
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input [14:0] F_ALMOST_EMPTY_OFFSET,
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// FIFO status signals
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output F_FULL,
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output F_EMPTY,
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output F_ALMOST_FULL,
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output F_ALMOST_EMPTY,
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output F_RD_ERROR,
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output F_WR_ERROR,
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output [15:0] F_RD_PTR,
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output [15:0] F_WR_PTR
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);
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// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
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parameter LOC = "UNPLACED";
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// Offset configuration
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parameter DYN_STAT_SELECT = 1'b0;
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parameter [14:0] ALMOST_FULL_OFFSET = 15'b0;
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parameter [14:0] ALMOST_EMPTY_OFFSET = 15'b0;
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// Port Widths
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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// RAM and Write Modes
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parameter RAM_MODE = "TDP"; // "TDP" or "SDP"
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parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"
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// Inverting Control Pins
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parameter A_CLK_INV = 1'b0;
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parameter B_CLK_INV = 1'b0;
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parameter A_EN_INV = 1'b0;
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parameter B_EN_INV = 1'b0;
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parameter A_WE_INV = 1'b0;
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parameter B_WE_INV = 1'b0;
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// Output Register
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parameter A_DO_REG = 1'b0;
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parameter B_DO_REG = 1'b0;
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// Error Checking and Correction
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parameter A_ECC_EN = 1'b0;
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parameter B_ECC_EN = 1'b0;
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integer i, k;
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// 512 x 80 bit
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reg [40959:0] memory = 40960'b0;
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reg [15:0] counter_max;
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reg [15:0] sram_depth;
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localparam tp = (A_WIDTH == 1) ? 15 :
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(A_WIDTH == 2) ? 14 :
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(A_WIDTH == 5) ? 13 :
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(A_WIDTH == 10) ? 12 :
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(A_WIDTH == 20) ? 11 :
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(A_WIDTH == 40) ? 10 : 9;
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initial begin
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// Check parameters
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if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin
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$display("ERROR: Illegal RAM MODE %d.", RAM_MODE);
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$finish();
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end
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if ((FIFO_MODE != "ASYNC") && (FIFO_MODE != "SYNC")) begin
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$display("ERROR: Illegal FIFO MODE %d.", FIFO_MODE);
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$finish();
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end
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if ((RAM_MODE == "SDP") && (DYN_STAT_SELECT == 1)) begin
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$display("ERROR: Dynamic offset configuration is not supported in %s mode.", RAM_MODE);
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$finish();
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end
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if ((RAM_MODE == "SDP") && ((A_WIDTH != 80) || (B_WIDTH != 80))) begin
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$display("ERROR: SDP is ony supported in 80 bit mode.");
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$finish();
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end
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if ((A_WIDTH == 80) && (RAM_MODE == "TDP")) begin
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$display("ERROR: Port A width of 80 bits is only supported in SDP mode.");
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$finish();
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end
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if ((B_WIDTH == 80) && (RAM_MODE == "TDP")) begin
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$display("ERROR: Port B width of 80 bits is only supported in SDP mode.");
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$finish();
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end
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if ((A_WIDTH != 80) && (A_WIDTH != 40) && (A_WIDTH != 20) && (A_WIDTH != 10) &&
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(A_WIDTH != 5) && (A_WIDTH != 2) && (A_WIDTH != 1) && (A_WIDTH != 0)) begin
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$display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, A_WIDTH);
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$finish();
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end
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if ((B_WIDTH != 80) && (B_WIDTH != 40) && (B_WIDTH != 20) && (B_WIDTH != 10) &&
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(B_WIDTH != 5) && (B_WIDTH != 2) && (B_WIDTH != 1) && (B_WIDTH != 0)) begin
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$display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, B_WIDTH);
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$finish();
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end
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if (A_WIDTH != B_WIDTH) begin
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$display("ERROR: The values of A_WIDTH and B_WIDTH must be equal.");
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end
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if ((A_ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (A_WIDTH != 40)) begin
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$display("ERROR: Illegal ECC Port A configuration. ECC mode requires TDP >=40 bit or SDP 80 bit, but is %s %d.", RAM_MODE, A_WIDTH);
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$finish();
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end
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// Set local parameters
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if (A_WIDTH == 1) begin // A_WIDTH=B_WIDTH
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counter_max = 2 * 32*1024 - 1;
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sram_depth = 32*1024;
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end
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else if (A_WIDTH == 2) begin
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counter_max = 2 * 16*1024 - 1;
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sram_depth = 16*1024;
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end
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else if (A_WIDTH == 5) begin
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counter_max = 2 * 8*1024 - 1;
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sram_depth = 8*1024;
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end
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else if (A_WIDTH == 10) begin
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counter_max = 2 * 4*1024 - 1;
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sram_depth = 4*1024;
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end
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else if (A_WIDTH == 20) begin
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counter_max = 2 * 2*1024 - 1;
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sram_depth = 2*1024;
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end
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else if (A_WIDTH == 40) begin
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counter_max = 2 * 1*1024 - 1;
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sram_depth = 1*1024;
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end
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else begin // 80 bit SDP
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counter_max = 2 * 512 - 1;
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sram_depth = 512;
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end
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end
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// Internal signals
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wire fifo_rdclk = A_CLK ^ A_CLK_INV;
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wire fifo_wrclk = (FIFO_MODE == "ASYNC") ? (B_CLK ^ B_CLK_INV) : (A_CLK ^ A_CLK_INV);
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wire [15:0] almost_full_offset = DYN_STAT_SELECT ? F_ALMOST_FULL_OFFSET : ALMOST_FULL_OFFSET;
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wire [15:0] almost_empty_offset = DYN_STAT_SELECT ? F_ALMOST_EMPTY_OFFSET : ALMOST_EMPTY_OFFSET;
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reg [39:0] A_DO_out = 0, A_DO_reg = 0;
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reg [39:0] B_DO_out = 0, B_DO_reg = 0;
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// Status signals
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reg fifo_full;
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reg fifo_empty;
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reg fifo_almost_full;
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reg fifo_almost_empty;
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assign F_FULL = fifo_full;
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assign F_EMPTY = fifo_empty;
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assign F_ALMOST_FULL = fifo_almost_full;
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assign F_ALMOST_EMPTY = fifo_almost_empty;
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assign F_WR_ERROR = (F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));
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assign F_RD_ERROR = (F_EMPTY && (A_EN ^ A_EN_INV));
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assign ram_we = (~F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV));
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assign ram_en = (~F_EMPTY && (A_EN ^ A_EN_INV));
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// Reset synchronizers
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reg [1:0] aclk_reset_q, bclk_reset_q;
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wire fifo_sync_rstn = aclk_reset_q;
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wire fifo_async_wrrstn = bclk_reset_q;
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wire fifo_async_rdrstn = aclk_reset_q;
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always @(posedge fifo_rdclk or negedge F_RST_N)
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begin
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if (F_RST_N == 1'b0) begin
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aclk_reset_q <= 2'b0;
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end
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else begin
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aclk_reset_q[1] <= aclk_reset_q[0];
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aclk_reset_q[0] <= 1'b1;
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end
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end
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always @(posedge fifo_wrclk or negedge F_RST_N)
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begin
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if (F_RST_N == 1'b0) begin
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bclk_reset_q <= 2'b0;
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end
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else begin
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bclk_reset_q[1] <= bclk_reset_q[0];
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bclk_reset_q[0] <= 1'b1;
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end
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end
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// Push/pop pointers
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reg [15:0] rd_pointer, rd_pointer_int;
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reg [15:0] wr_pointer, wr_pointer_int;
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reg [15:0] rd_pointer_cmp, wr_pointer_cmp;
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wire [15:0] rd_pointer_nxt;
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wire [15:0] wr_pointer_nxt;
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reg [15:0] fifo_rdaddr, rdaddr;
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reg [15:0] fifo_wraddr, wraddr;
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assign F_RD_PTR = fifo_rdaddr;
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assign F_WR_PTR = fifo_wraddr;
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always @(posedge fifo_rdclk or negedge F_RST_N)
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begin
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if (F_RST_N == 1'b0) begin
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rd_pointer <= 0;
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rd_pointer_int <= 0;
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end
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else if (ram_en) begin
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rd_pointer <= rd_pointer_nxt;
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rd_pointer_int <= rd_pointer_nxt[15:1] ^ rd_pointer_nxt[14:0];
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end
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end
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assign rd_pointer_nxt = (rd_pointer == counter_max) ? (0) : (rd_pointer + 1'b1);
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always @(posedge fifo_wrclk or negedge F_RST_N)
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begin
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if (F_RST_N == 1'b0) begin
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wr_pointer <= 0;
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wr_pointer_int <= 0;
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end
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else if (ram_we) begin
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wr_pointer <= wr_pointer_nxt;
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wr_pointer_int <= wr_pointer_nxt[15:1] ^ wr_pointer_nxt[14:0];
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end
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end
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assign wr_pointer_nxt = (wr_pointer == counter_max) ? (0) : (wr_pointer + 1'b1);
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// Address synchronizers
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reg [15:0] rd_pointer_sync, wr_pointer_sync;
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reg [15:0] rd_pointer_sync_0, rd_pointer_sync_1;
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reg [15:0] wr_pointer_sync_0, wr_pointer_sync_1;
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always @(posedge fifo_rdclk or negedge F_RST_N)
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begin
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if (F_RST_N == 1'b0) begin
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wr_pointer_sync_0 <= 0;
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wr_pointer_sync_1 <= 0;
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end
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else begin
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wr_pointer_sync_0 <= wraddr;
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wr_pointer_sync_1 <= wr_pointer_sync_0;
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end
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end
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always @(posedge fifo_wrclk or negedge F_RST_N)
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begin
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if (F_RST_N == 1'b0) begin
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rd_pointer_sync_0 <= 0;
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rd_pointer_sync_1 <= 0;
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end
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else begin
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rd_pointer_sync_0 <= rdaddr;
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rd_pointer_sync_1 <= rd_pointer_sync_0;
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end
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end
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always @(*) begin
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fifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}};
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fifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}};
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rdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]};
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wraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]};
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if (FIFO_MODE == "ASYNC")
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fifo_full = (wraddr[tp-2:0] == rd_pointer_sync_1[tp-2:0] ) && (wraddr[tp] != rd_pointer_sync_1[tp] ) && ( wraddr[tp-1] != rd_pointer_sync_1[tp-1] );
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else
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fifo_full = (wr_pointer[tp-1:0] == rd_pointer[tp-1:0]) && (wr_pointer[tp] ^ rd_pointer[tp]);
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if (FIFO_MODE == "ASYNC")
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fifo_empty = (wr_pointer_sync_1[tp:0] == rdaddr[tp:0]);
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else
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fifo_empty = (wr_pointer[tp:0] == rd_pointer[tp:0]);
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rd_pointer_cmp = (FIFO_MODE == "ASYNC") ? rd_pointer_sync : rd_pointer;
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if (wr_pointer[tp] == rd_pointer_cmp[tp])
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fifo_almost_full = ((wr_pointer[tp-1:0] - rd_pointer_cmp[tp-1:0]) >= (sram_depth - almost_full_offset));
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else
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fifo_almost_full = ((rd_pointer_cmp[tp-1:0] - wr_pointer[tp-1:0]) <= almost_full_offset);
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wr_pointer_cmp = (FIFO_MODE == "ASYNC") ? wr_pointer_sync : wr_pointer;
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if (wr_pointer_cmp[tp] == rd_pointer[tp])
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fifo_almost_empty = ((wr_pointer_cmp[tp-1:0] - rd_pointer[tp-1:0]) <= almost_empty_offset);
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else
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fifo_almost_empty = ((rd_pointer[tp-1:0] - wr_pointer_cmp[tp-1:0]) >= (sram_depth - almost_empty_offset));
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end
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generate
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always @(*) begin
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wr_pointer_sync = 0;
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rd_pointer_sync = 0;
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for (i=tp; i >= 0; i=i-1) begin
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if (i == tp) begin
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wr_pointer_sync[i] = wr_pointer_sync_1[i];
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rd_pointer_sync[i] = rd_pointer_sync_1[i];
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end
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else begin
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wr_pointer_sync[i] = wr_pointer_sync_1[i] ^ wr_pointer_sync[i+1];
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rd_pointer_sync[i] = rd_pointer_sync_1[i] ^ rd_pointer_sync[i+1];
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end
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end
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end
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if (RAM_MODE == "SDP") begin
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// SDP push ports A+B
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always @(posedge fifo_wrclk)
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begin
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for (k=0; k < A_WIDTH; k=k+1) begin
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if (k < 40) begin
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if (ram_we && A_BM[k]) memory[fifo_wraddr+k] <= A_DI[k];
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end
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else begin // use both ports
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if (ram_we && B_BM[k-40]) memory[fifo_wraddr+k] <= B_DI[k-40];
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end
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end
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end
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// SDP pop ports A+B
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always @(posedge fifo_rdclk)
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begin
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for (k=0; k < B_WIDTH; k=k+1) begin
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if (k < 40) begin
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if (ram_en) A_DO_out[k] <= memory[fifo_rdaddr+k];
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end
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else begin // use both ports
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if (ram_en) B_DO_out[k-40] <= memory[fifo_rdaddr+k];
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end
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end
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end
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end
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else if (RAM_MODE == "TDP") begin
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// TDP pop port A
|
||||
always @(posedge fifo_rdclk)
|
||||
begin
|
||||
for (i=0; i < A_WIDTH; i=i+1) begin
|
||||
if (ram_en) begin
|
||||
A_DO_out[i] <= memory[fifo_rdaddr+i];
|
||||
end
|
||||
end
|
||||
end
|
||||
// TDP push port B
|
||||
always @(posedge fifo_wrclk)
|
||||
begin
|
||||
for (i=0; i < B_WIDTH; i=i+1) begin
|
||||
if (ram_we && B_BM[i])
|
||||
memory[fifo_wraddr+i] <= B_DI[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Optional output register
|
||||
generate
|
||||
if (A_DO_REG) begin
|
||||
always @(posedge fifo_rdclk) begin
|
||||
A_DO_reg <= A_DO_out;
|
||||
end
|
||||
assign A_DO = A_DO_reg;
|
||||
end
|
||||
else begin
|
||||
assign A_DO = A_DO_out;
|
||||
end
|
||||
if (B_DO_REG) begin
|
||||
always @(posedge fifo_rdclk) begin
|
||||
B_DO_reg <= B_DO_out;
|
||||
end
|
||||
assign B_DO = B_DO_reg;
|
||||
end
|
||||
else begin
|
||||
assign B_DO = B_DO_out;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
// Models of the LUT2 tree primitives
|
||||
module CC_L2T4(
|
||||
output O,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue