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Organizing Speedster file names

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This commit is contained in:
dh73 2017-11-08 20:23:55 -06:00
parent adf1754729
commit 1fc061d90c
5 changed files with 4 additions and 4 deletions
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4
techlibs/achronix/Makefile.inc
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@ -1,6 +1,6 @@
OBJS += techlibs/achronix/synth_speedster.o OBJS += techlibs/achronix/synth_speedster.o
$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_comb_speedster.v)) $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map_speedster.v)) $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))

0
techlibs/achronix/speedster22i/cells_arith_speedster.v → techlibs/achronix/speedster22i/cells_arith.v
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0
techlibs/achronix/speedster22i/cells_map_speedster.v → techlibs/achronix/speedster22i/cells_map.v
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0
techlibs/achronix/speedster22i/cells_comb_speedster.v → techlibs/achronix/speedster22i/cells_sim.v
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4
techlibs/achronix/synth_speedster.cc
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@ -122,7 +122,7 @@ struct SynthIntelPass : public ScriptPass {
{ {
if (check_label("begin")) if (check_label("begin"))
{ {
run("read_verilog -sv -lib +/achronix/speedster22i/cells_comb_speedster.v"); run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
} }
@ -164,7 +164,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("map_cells")) if (check_label("map_cells"))
{ {
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I"); run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
run("techmap -map +/achronix/speedster22i/cells_map_speedster.v"); run("techmap -map +/achronix/speedster22i/cells_map.v");
run("dffinit -ff dffeas Q INIT"); run("dffinit -ff dffeas Q INIT");
run("clean -purge"); run("clean -purge");
} }